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參數(shù)資料
| 型號(hào)： | AM79C961A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | PCnet⑩- 2跳線的ISA，全雙工單芯片以太網(wǎng)控制器為ISA |
| 文件頁數(shù)： | 29/85頁 |
| 文件大?。?/td> | 1088K |
| 代理商： | AM79C961A |
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Am79C961A
29
P R E L I M I N A R Y
PRDB1/EEDI
Private Data Bus Bit 1/Data In
A multifunction pin which serves as PRDB1 of the
private data bus and, when ISACSR3 bit 4 is set,
changes to become DATA In to the EEPROM.
PRDB0/EESK
Private Data Bus Bit 0/
Serial Clock
A multifunction pin which serves as PRDB0 of the
private data bus and, when ISACSR3 bit 4 is set,
changes to become Serial Clock to the EEPROM.
SHFBUSY
Shift Busy
This pin indicates that a read from the external
EEPROM is in progress. It is active only when data is
being shifted out of the EEPROM due to a hardware
RESET or assertion of the EE_LOAD bit (ISACSR3, bit
14). If this pin is left unconnected or pulled low with a
pull-down resistor, an EEPROM checksum error is
forced. Normally, this pin should be connected to V
CC
through a 10K
pull-up resistor.
EECS
EEPROM CHIP SELECT
This signal is asserted when read or write accesses
are being performed to the EEPROM. It is controlled by
ISACSR3. It is driven at Reset during EEPROM Read.
SLEEP
Sleep
When SLEEP input is asserted (active LOW), the
PCnet-ISA II controller performs an internal system
reset and proceeds into a power savings mode. All out-
puts will be placed in their normal reset condition. All
PCnet-ISA II controller inputs will be ignored except for
the SLEEP pin itself. Deassertion of SLEEP results in
the device waking up. The system must delay the
starting of the network controller by 0.5 seconds to
allow internal analog circuits to stabilize.
SMA
Slave Mode Architecture
This pin must be permanently pulled LOW for operation
in the Bus Slave mode. It is sampled after the hardware
RESET sequence. In the Bus Slave mode, the
PCnet-ISA II can be programmed for Shared Memory
Input/Output
Input/Output
Input/Output
Output
Input
Input
access or Programmed I/O access through the
PIOSEL bit (ISACSR2, bit 13).
SMAM
Shared Memory
Address Match
When the Shared Memory architecture is selected
(ISACSR2, bit 13), this pin is an input that indicates an
access to shared memory when asserted. The type of
access is decided by MEMR or MEMW.
Input
When the Programmed I/O architecture is selected,
this pin should be permanently tied HIGH.
SROE
Static RAM Output Enable
This pin directly controls the external SRAM’s OE pin.
SRCS/IRQ12
Static RAM Chip Select
This pin directly controls the external SRAM’s chip
select (CS) pin when the Flash boot ROM option is
selected.
Output
Output
When Flash boot ROM option is not selected, this pin
becomes IRQ12.
SRWE/WE
Static RAM Write Enable/
Write Enable
This pin (SRWE) directly controls the external SRAM’s
WE pin when a Flash memory device is not
implemented.
Output
When a Flash memory device is implemented, this pin
becomes a global write enable (WE) pin.
XTAL1
Crystal Connection
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. Alternatively, an
external 20 MHz CMOS-compatible clock signal can be
used to drive this pin. Refer to the section on External
Crystal Characteristics for more details.
XTAL2
Crystal Connection
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. If an external
clock is used, this pin should be left unconnected.
Input
Output
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| AM79C961A_00 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
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| AM79C961AKC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C961AKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
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