參數(shù)資料
型號: AM79C961A
廠商: Advanced Micro Devices, Inc.
英文描述: PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述: PCnet⑩- 2跳線的ISA,全雙工單芯片以太網(wǎng)控制器為ISA
文件頁數(shù): 19/85頁
文件大小: 1088K
代理商: AM79C961A
Am79C961A
19
P R E L I M I N A R Y
SHFBUSY
Shift Busy
This pin indicates that a read from the external
EEPROM is in progress. It is active only when data is
being shifted out of the EEPROM due to a hardware
RESET or assertion of the EE_LOAD bit (ISACSR3, bit
14). If this pin is left unconnected or pulled low with a
pull-down resistor, an EEPROM checksum error is
forced. Normally, this pin should be connected to V
CC
through a 10K
pull-up resistor.
EECS
EEPROM CHIP SELECT
This signal is asserted when read or write accesses
are being performed to the EEPROM. It is controlled by
ISACSR3. It is driven at Reset during EEPROM Read.
SLEEP
Sleep
When SLEEP pin is asserted (active LOW), the
PCnet-ISA II controller performs an internal system
reset and proceeds into a power savings mode. All
Input/Output
Output
Input
outputs will be placed in their normal reset condition.
All PCnet-ISA II controller inputs will be ignored except
for the SLEEP pin itself. Deassertion of SLEEP results
in the device waking up. The system must delay the
starting of the network controller by 0.5 seconds to
allow internal analog circuits to stabilize.
XTAL1
Crystal Connection
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. Alternatively, an
external 20 MHz CMOS-compatible clock signal can be
used to drive this pin. Refer to the section on External
Crystal Characteristics for more details.
XTAL2
Crystal Connection
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. If an external
clock is used, this pin should be left unconnected.
Input
Output
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