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| 型號(hào)： | AM79C940VCW |
| 廠(chǎng)商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | Media Access Controller for Ethernet (MACE) |
| 中文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁(yè)數(shù)： | 44/122頁(yè) |
| 文件大?。?/td> | 914K |
| 代理商： | AM79C940VCW |
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AMD
44
Am79C940
internal MENDEC activity), and allow the RXCRS pin to
indicate the current state of the RXD
±
pair. If there is no
receive activity on RXD
±
, only CLSN will be active dur-
ing jabber detect. If there is RXD
±
activity, both CLSN
and RXCRS will be active.
External Address Detection Interface
(EADI)
This interface is provided to allow external perfect ad-
dress filtering This feature is typically utilized for termi-
nal server, bridge and/or router type products. The use
of external logic is required, to capture the serial bit
stream from the MACE device, and compare this with a
table of stored addresses or identifiers. See the EADI
port diagram in the Systems Applications section, Net-
work Interfaces sub-section, for details.
The EADI interface operates directly from the NRZ de-
coded data and clock recovered by the Manchester
decoder. This allows the external address detection to
be performed in parallel with frame reception and ad-
dress comparison in the MAC Station Address Detec-
tion (SAD) block.
SRDCLK is provided to allow clocking of the receive bit
stream from the MACE device, into the external address
detection logic. Once a received packet commences
and data and clock are available from the decoder, the
EADI interface logic will monitor the alternating (1,0)
preamble pattern until the two ones of the Start Frame
Delimiter (1,0,1,0,1,0,1,1) are detected, at which point
the SF/BD output will be driven high.
After SF/BD is asserted the serial data from SRD should
be de-serialized and sent to a Content Addressable
Memory (CAM) or other address detection device.
To allow simple serial to parallel conversion, SF/BD is
provided as a strobe and/or marker to indicate the de-
lineation of bytes, subsequent to the SFD. This feature
provides a mechanism to allow not only capture and/or
decoding of the physical or logical (group) address, but
also facilitates the capture of header information to de-
termine protocol and or inter-networking information.
The
EAM/R
pin is driven by the external address com-
parison logic, to either reject or accept the packet. Two
alternative modes are permitted, allowing the external
logic to either accept the packet based on address
match, or reject the packet if there is no match. The two
alternate methods are programmed using the Match/
Reject (M/
R
) bit in the Receive Frame Control register.
If the M/
R
bit is set, the pin is configured as
EAM
(Exter-
nal Address Match). The MACE device can be config-
ured with Physical, Logical or Broadcast Address
comparison operational. If an internal address match is
detected, the packet will be accepted regardless of the
condition of
EAM
. Additional addresses can be located
in the external address detection logic. If a match is de-
tected,
EAM
must go active within 600 ns of the last bit in
the destination address field (end of byte 6) being pre-
sented on the SRD output, to guarantee frame recep-
tion. In addition,
EAM
must go inactive after a match has
been detected on a previous packet, before the next
match can take place on any subsequent packet.
EAM
must be asserted for a minimum pulse width of 200 ns.
If the M/
R
bit is clear (default state after either the
RESET
pin or SWRST bit have been activated), the pin
is configured as
EAR
(External Address Reject). The
MACE device can be configured with Physical, Logical
or Broadcast Address comparison operational. If an in-
ternal address match is detected, the packet will be ac-
cepted regardless of the condition of
EAR
. Incoming
packets which do not pass the internal address compari-
son will continue to be received by the MACE device.
EAR
must be externally presented to the MACE chip
prior to the first assertion of
RDTREQ
, to guarantee re-
jection of unwanted packets. This allows approximately
58 byte times after the last destination address bit is
available to generate the
EAR
signal, assuming the
MACE device is not configured to accept runt packets.
EAR
will be ignored by the MACE device from 64 byte
times after the SFD, and the packet will be accepted if
EAR
has not been asserted before this time. If the
MACE device is configured to accept runt packets, the
EAR
signal must be generated prior to the receive mes-
sage completion, which could be as short as 12 byte
times (assuming six bytes for source address, two bytes
for length, no data, four bytes for FCS) after the last bit
of the destination address is available.
EAR
must have a
pulse width of at least 200 ns.
Note that setting the PROM bit (MAC Configuration
Control) will cause all receive packets to be received, re-
gardless of the programming of M/
R
or the state of the
EAM/R
input. The following table summarizes the op-
eration of the EADI features.
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