參數(shù)資料
型號： AM79C940VCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： Media Access Controller for Ethernet (MACE)
中文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP80
封裝： TQFP-80
文件頁數(shù)： 33/122頁
文件大?。?/td> 914K
代理商： AM79C940VCW
AMD
33
Am79C940
The first assertion of
RDTREQ
for a packet will occur af-
ter the longer of the following two conditions is met:
I
ets and packets experiencing collision within the slot
time will be rejected).
64-bytes have been received (to assure runt pack-
I
12 bytes. The additional 12 bytes are necessary to en-
sure that any permutation of byte/word read access is
The RCVFW threshold is reached plus an additional
guaranteed. They are required for all threshold values,
but in the case of the 16 and 32-byte thresholds, the re-
quirement that the slot time criteria is met dominates.
Any subsequent assertion of
RDTREQ
necessary to
complete the transfer of the packet will occur after the
RCVFW threshold is reached plus an additional 12
bytes. The table below also outlines the latency pro-
vided by the MACE device when the
RDTREQ
is
asserted.
Receive FIFO Watermarks,
RDTREQ
Assertion and Latency
Bytes Required for
First Assertion of
RDTREQ
64
64
76
XX
Bytes of Latency
After First Assertion
of
RDTREQ
64
64
52
XX
Bytes Required for
Subsequent Assertion
of
RDTREQ
28
44
76
XX
Bytes of Latency After
Subsequent Assertion
of
RDTREQ
100
84
52
XX
RCVFW
[1–0]
00
01
10
11
Receive FIFO—Burst Operation:
The RCVFIFO also provides a burst mode capability,
programmed by the RCVBRST bit in the FIFO Configu-
ration Control register, to modify the operation of
RDTREQ
.The assertion of
RDTREQ
will occur accord-
ing to the programming of the RCVFW bits.
RDTREQ
will be de-asserted when the RCVFIFO can only provide
a single read cycle (one word read). This allows the ex-
ternal device to burstdata from the RCVFIFO once
RDTREQ
is asserted, and stop when
RDTREQ
is
deasserted.
Receive FIFO—Low Latency Receive Operation:
The LOW Latency Receive mode can be programmed
using the Low Latency Receive bit (LLRCV in the Re-
ceive Frame Control register). This effectively causes
the assertion of
RDTREQ
to be directly coupled to the
low watermark of 12 bytes in the RCVFIFO. Once the
12-byte threshold is reached (plus some internal syn-
chronization delay of less than 1 byte),
RDTREQ
will be
asserted, and will remain active until the RCVFIFO can
support only one read cycle (one word of data), as in the
burst operation described earlier.
The intended use for the Low Latency Receive mode is
to allow fast forwarding of a received packet in a bridge
application. In this case, the receiving process is made
aware of the receive packet after only 9.6
μ
s, instead of
waiting up to 60.8
μ
s (76-bytes) necessary for the initial
assertion of
RDTREQ
. An Ethernet-to-Ethernet bridge
employing the MACE device (on all the Ethernet con-
nections) with the XMTSP of all MACE controller
XMTFIFOs set to the minimum (4-bytes), forwarding of
a receive packet can be achieved within a sub 20
μ
s de-
lay including processing overhead.
Note however that this mode places significant burden
on the host processor. The receiving MACE device will
no longer delete runt packets. A runt packet will have the
Receive Frame Status appended to the receive data
which the host must read as normal. The MACE device
will not attempt to delete runt packets from the
RCVFIFO in the Low Latency Receive mode. Collision
fragments will also be passed to the host if they are de-
tected after the 12-byte threshold has been reached. If a
collision occurs, the Receive Frame Status (RCVFS)
will be appended to the data successfully received in the
RCVFIFO up to the point the collision was detected. No
additional receive data will be written to the RCVFIFO.
Note that the RCVFS will not become available until af-
ter the receive activity ceases. The collision indication
(CLSN) in the Receive Status (RCVSTS) will be set, and
the Receive Message Byte Count (RCVCNT) will be the
correct count of the total duration of activity, including
the period that collision was detected. The detection of
normal (slot time) collisions versus late collisions can
only be made by counting the number of bytes that were
successfully received prior to the termination of the
packet data.
In all cases where the reception ends prematurely (runt
or collision), the data that was successfully received
prior to the termination of reception must be read from
the RCVFIFO before the RCVFS bytes are available.
Media Access Control (MAC)
The Media Access Control engine is the heart of the
MACE device, incorporating the essential protocol re-
quirements for operation of a compliant Ethernet/802.3
node, and providing the interface between the FIFO
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