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參數(shù)資料
| 型號： | AM79C940VCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Media Access Controller for Ethernet (MACE) |
| 中文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁數(shù)： | 22/122頁 |
| 文件大?。?/td> | 914K |
| 代理商： | AM79C940VCW |
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AMD
22
Am79C940
DXCVR Configuration—Normal Operation
SLEEP
Pin
ASEL
Bit
LNKST
Pin
PORTSEL
[1–0] Bits
ENPLSIO
Bit
Interface
Description
Pin
Function
1
X
X
XX
X
SIA Test Mode
High
Impedance
LOW
HIGH
HIGH
LOW
LOW
HIGH
1
1
1
1
1
1
0
0
0
0
1
1
X
X
X
X
00
01
10
11
0X
0X
X
X
X
X
X
X
AUI
10BASE-T
DAI Port
GPSI
AUI
10BASE-T
HIGH
LOW
Note:
RWAKE and ASEL are located in the PHY Configuration Control register (REG ADDR 15). PORTSEL [1–0] and
ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).
10BASE-T Interface
TXD+, TXD–
Transmit Data (Output)
10BASE-T port differential drivers.
TXP+, TXP–
Transmit Pre-Distortion (Output)
Transmit wave form differential driver for pre-distortion.
RXD+, RXD–
Receive Data (Input)
10BASE-T port differential receiver. These pins should
be externally terminated to reduce power consumption if
the 10BASE-T interface is not used.
LNKST
Link Status (OutputOpen Drain)
This pin is driven LOW if the link is identified as func-
tional. If the link is determined to be nonfunctional, due
to missing idle link pulses or data packets, then this pin
is not driven (requires external pull-up). In the LOW out-
put state, the pin is capable of sinking a maximum of
12 mA and can be used to drive an LED.
This feature can be disabled by setting the Disable Link
Test (DLNKTST) bit in the PHY Configuration Control
register. In this case the internal Link Test Receive func-
tion is disabled, the
LNKST
pin will be driven LOW, and
the Transmit and Receive functions will remain active
regardless of arriving idle link pulses and data. The in-
ternal 10BASE-T MAU will continue to generate idle link
pulses irrespective of the status of the DLNKTST bit.
RXPOL
Receive Polarity (Output,Open Drain)
The twisted pair receiver is capable of detecting a re-
ceive signal with reversed polarity (wiring error). The
RXPOL
pin is normally in the LOW state, indicating cor-
rect polarity of the received signal. If the receiver detects
a received packet with reversed polarity, then this pin is
not driven (requires external pull–up) and the polarity of
subsequent packets are inverted. In the LOW output
state, this pin is capable of sinking a maximum of 12mA
and can be used to drive an LED.
The polarity correction feature can be disabled by set-
ting the Disable Auto Polarity Correction (DAPC) bit in
the PHY Configuration Control register. In this case, the
Receive Polarity correction circuit is disabled and the in-
ternal receive signal remains non-inverted, irrespective
of the received signal. Note that
RXPOL
will continue to
reflect the polarity detected by the receiver.
General Purpose Serial Interface (GPSI)
STDCLK
Serial Transmit Data Clock (Input/Output)
When either the AUI, 10BASE-T or DAI port is selected,
STDCLK is an output operating at one half the crystal or
XTAL1 frequency. STDCLK is the encoding clock for
Manchester data transferred to the output of either the
AUI DO
±
pair, the 10BASE-T TXD
±
/TXP
±
pairs, or the
DAI port TXDAT
±
pair. When using the GPSI port,
STDCLK is an input at the network data rate, provided
by the external Manchester encode/decoder, to strobe
out the NRZ data presented on the TXDAT+ output.
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