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| 型號(hào)： | AM79C940KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | Media Access Controller for Ethernet (MACE) |
| 中文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP10 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 58/122頁(yè) |
| 文件大小： | 914K |
| 代理商： | AM79C940KCW |
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AMD
58
Am79C940
activation of the
RESET
pin or
SWRST bit. DXMTFCS is sam-
pled only when
EOF
is asserted
during a Transmit FIFO write.
Bit
Name
Description
Bit 2–1 RES
Reserved. Read as zeroes. Al-
ways write as zeroes.
APAD XMT Auto Pad Transmit. APAD XMT
enables the automatic padding
feature. Transmit frames will be
padded to extend them to 64
bytes including FCS. The FCS is
calculated for the entire frame in-
cluding pad, and appended after
the pad field. APAD XMT will
override the programming of the
DXMTFCS bit. APAD XMT is set
by activation of the
RESET
pin or
SWRST bit. APAD XMT is sam-
pled only when
EOF
is asserted
during a Transmit FIFO write.
Bit 0
Transmit Frame Status (XMTFS)
The Transmit Frame Status is valid when the XMTSV bit
is set. The register is read only, and is cleared when
XMTSV is set and a read operation is performed. The
XMTINT bit in the Interrupt Register will be set when any
bit is set in this register.
(REG ADDR 3)
Note that if XMTSV is not set, the values in this register
can change at any time, including during a read opera-
tion. This register should be read after the Transmit Re-
try Count (XMTRC). See the description of the Transmit
Retry Count (XMTRC) for additional details.
XMTSV
LCOL
MORE
ONE
DEFER
LCAR
UFLO
RTRY
Bit
Name
Description
Bit 7
XMTSV
Transmit Status Valid. Transmit
Status Valid indicates that this
status is valid for the last frame
transmitted. The value of XMTSV
will not change during a read op-
eration.
Underflow. Indicates that the
Transmit FIFO emptied before
the end of frame was reached.
The transmitted frame is trun-
cated at that point. If UFLO is set,
TDTREQ
will be de-asserted,
and will not be re-asserted until
the XMTFS has been read.
Bit 6
UFLO
Bit 5
LCOL
Late Collision. Indicates that a
collision occurred after the slot
time of the channel elapsed. If
LCOL is set,
TDTREQ
will be de-
asserted, and will not be
re-asserted until the XMTFS has
been read. The MACE device
does not retry after a late
collision.
More. Indicates that more than
one retry was needed to transmit
the frame. ONE, MORE and
RTRY are mutually exclusive.
One. Indicates that exactly one
retry was needed to transmit the
frame. ONE, MORE and RTRY
are mutually exclusive.
Defer. Indicates that MACE de-
vice had to defer transmission of
the frame. This condition results
if the channel is busy when the
MACE device is ready to
transmit.
Loss of Carrier. Indicates that the
carrier became false during a
transmission. The MACE device
does not retry upon Loss of Car-
rier. LCAR will not be set when
the DAI port is selected, when
the 10BASE-T port is selected
and in the link pass state, or dur-
ing any internal loopback mode.
When the 10BASE-T port is se-
lected and in the link fail state,
LCAR will will be reported for any
transmission attempt.
Retry Error. Indicates that all at-
tempts to transmit the frame
were unsuccessful, and that fur-
ther attempts have been aborted.
If Disable Retry (DRTRY in the
Transmit Frame Control register)
is cleared, RTRY will be set when
a total of 16 unsuccessful at-
tempts were made to transmit the
frame. If DRTRY is set, RTRY in-
dicates that the first and only at-
tempt to transmit the frame was
unsuccessful. ONE, MORE and
RTRY are mutually exclusive. If
RTRY is set,
TDTREQ
will be de-
asserted, and will not be re-
asserted until the XMTFS has
been read.
Bit 4
MORE
Bit 3
ONE
Bit 2
DEFER
Bit 1
LCAR
Bit 0
RTRY
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