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參數(shù)資料
| 型號： | AM79C940KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Media Access Controller for Ethernet (MACE) |
| 中文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP10 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 19/122頁 |
| 文件大?。?/td> | 914K |
| 代理商： | AM79C940KCW |
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AMD
19
Am79C940
PIN DESCRIPTION
Network Interfaces
The MACE device has five potential network interfaces.
Only one of the interfaces that provides physical net-
work attachment can be used (active) at any time. Se-
lection between the AUI, 10BASE-T, DAI or GPSI ports
is provided by programming the PHY Configuration
Control register. The EADI port is effectively active at all
times. Some signals, primarily used for status reporting,
are active for more than one single interface (the CLSN
pin for instance). Under each of the descriptions for the
network interfaces, the primary signals which are
unique to that interface are described. Where signals
are active for multiple interfaces, they are described
once under the interface most appropriate.
Attachment Unit Interface (AUI)
CI+/CI
Control In (Input)
A differential input pair, signalling the MACE device that
a collision has been detected on the network media, in-
dicated by the CI
±
inputs being exercised with 10 MHz
pattern of sufficient amplitude and duration. Operates at
pseudo-ECL levels.
DI+/DI
Data In (Input)
A differential input pair to the MACE device for receiving
Manchester encoded data from the network. Operates
at pseudo-ECL levels.
DO+/DO
Data Out (Output)
A differential output pair from the MACE device for
transmitting Manchester encoded data to the network.
Operates at pseudo-ECL levels.
Digital Attachment Interface (DAI)
TXDAT+/TXDAT–
Transmit Data (Output)
When the DAI port is selected, TXDAT
±
are configured
as a complementary pair for Manchester encoded data
output from the MACE device, used to transmit data to a
local external network transceiver. During valid trans-
mission (indicated by
TXEN
low), a logical 1is indicated
by the TXDAT+ pin being in the high state and TXDAT–
in the low state; and a logical 0is indicated by the
TXDAT+ pin being in the low state and TXDAT– in the
high state. During idle (
TXEN
high), TXDAT+ will be in
the high state, and TXDAT– in the low state. When the
GPSI port is selected, TXDAT+ will provide NRZ data
output from the MAC core, and TXDAT– will be held in
the LOW state. Operates at TTL levels. The operations
of TXDAT+ and TXDAT– are defined in the following
tables:
TXDAT+ Configuration
PORTSEL
[1–0]
SLEEP
ENPLSIO
Interface Description
Pin Function
0
1
1
1
1
1
XX
00
01
10
11
XX
X
1
1
1
1
0
Sleep Mode
AUI
10BASE-T
DAI Port
GPSI
Status Disabled
High Impedance
High Impedance (Note 2)
High Impedance (Note 2)
TXDAT+ Output
TXDAT+ Output
High Impedance (Note 2)
TXDAT– Configuration
PORTSEL
[1–0]
SLEEP
ENPLSIO
Interface Description
Pin Function
0
1
1
1
1
1
XX
00
01
10
11
XX
X
1
1
1
1
0
Sleep Mode
AUI
10BASE-T
DAI Port
GPSI
Status Disabled
High Impedance
High Impedance
High Impedance
TXDAT– Output
LOW
High Impedance
Notes:
1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).
2. This pin should be externally terminated, if unused, to reduce power consumption.
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