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參數(shù)資料
| 型號： | Am70PDL127CDH85IT |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| 中文描述： | 2 × 64兆位（8米× 16位）的CMOS 3.0伏特，只有頁面模式閃存數(shù)據(jù)存儲128兆位（8米× 16位）的CMOS |
| 文件頁數(shù)： | 104/127頁 |
| 文件大?。?/td> | 849K |
| 代理商： | AM70PDL127CDH85IT |
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102
Am70PDL127CDH/Am70PDL129CDH
November 24, 2003
A D V A N C E I N F O R M A T I O N
Command Definitions
Table 9.
Command Definitions (x16 Mode)
Legend:
X = Don’t care
RA = Read Address of memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address . Addresses latch on falling edge of WE# or CE#
pulse, whichever happens later.
PD = Program Data for location PA. Data latches on rising edge of WE#
or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within same write buffer
page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1.
2.
3.
4.
See
Table 1
for description of bus operations.
All values are in hexadecimal.
Shaded cells indicate read cycles. All others are write cycles.
During unlock and command cycles, when lower address bits are
555 or 2AA as shown in table, address bits above A11 and data
bits above DQ7 are don’t care.
No unlock or command cycles required when device is in read
mode.
Reset command is required to return to read mode (or to
erase-suspend-read mode if previously in Erase Suspend) when
device is in autoselect mode, or if DQ5 goes high while device is
providing status information.
Fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. Except for RD, PD
and WC. See
Autoselect Command Sequence
section for more
information.
Device ID must be read in three cycles.
5.
6.
7.
8.
9.
WP# protects highest address sector, data is 98h for factory
locked and 18h for not factory locked. Data is 00h for an
unprotected sector group and 01h for a protected sector group.
10. Total number of cycles in command sequence is determined by
number of words written to write buffer. Maximum number of
cycles in command sequence is 21.
11. Command sequence resets device for next command after
aborted write-to-buffer operation.
12. Unlock Bypass command is required prior to Unlock Bypass
Program command.
13. Unlock Bypass Reset command is required to return to read
mode when device is in unlock bypass mode.
14. System may read and program in non-erasing sectors, or enter
autoselect mode, when in Erase Suspend mode. Erase Suspend
command is valid only during a sector erase operation.
15. Erase Resume command is valid only during Erase Suspend
mode.
16. Command is valid when device is ready to read array data or when
device is in autoselect mode.
Command
Sequence
(Note 1)
C
Bus Cycles (Notes 2–5)
Third
Addr
Data
First
Second
Addr
Fourth
Fifth
Sixth
Addr
RA
XXX
555
555
Data
RD
F0
AA
AA
Data
Addr
Data
Addr
Data
Addr
Data
Read (Note 5)
Reset (Note 6)
Manufacturer ID
Device ID (Note 8)
SecSi
Sector Factory Protect
(Note 9)
1
1
4
6
A
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
Write to Buffer (Note 11)
Program Buffer to Flash
Write to Buffer Abort Reset (Note 12)
Unlock Bypass
Unlock Bypass Program (Note 13)
Unlock Bypass Reset (Note 14)
Chip Erase
Sector Erase
Program/Erase Suspend (Note 15)
Program/Erase Resume (Note 16)
CFI Query (Note 17)
2AA
2AA
55
55
555
555
90
90
X00
X01
0001
227E
X0E
220C
X0F
2201
4
555
AA
2AA
55
555
90
X03
(Note 10)
Sector Group Protect Verify
(Note 10)
4
555
AA
2AA
55
555
90
(SA)X02
00/01
3
4
4
6
1
3
3
2
2
6
6
1
1
1
555
555
555
555
SA
555
555
XXX
XXX
555
555
BA
BA
55
AA
AA
AA
AA
29
AA
AA
A0
90
AA
AA
B0
30
98
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
SA
88
90
A0
25
XXX
PA
SA
00
PD
WC
PA
PD
WBL
PD
2AA
2AA
PA
XXX
2AA
2AA
55
55
PD
00
55
55
555
555
F0
20
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
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| Am70PDL129CDH | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| Am70PDL129CDH66IS | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| Am70PDL129CDH66IT | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
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| Am70PDL129CDH85IT | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AM70PDL129BDH | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| AM70PDL129BDH66I | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL129BDH66IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| AM70PDL129BDH66IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| AM70PDL129BDH85I | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
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