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參數(shù)資料
| 型號(hào)： | AM5X86 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能單片32位微處理器) |
| 中文描述： | 高性能設(shè)計(jì)的片上集成完整的32位架構(gòu)Micrprocessor（高性能單片32位微處理器） |
| 文件頁(yè)數(shù)： | 38/67頁(yè) |
| 文件大?。?/td> | 1201K |
| 代理商： | AM5X86 |
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38
Am5
X
86 Microprocessor
AMD
PRELIMINARY
Figure 20. Stop Clock State Machine
(valid for Write-back mode only)
Figure 21. Recognition of Inputs when Exiting Stop Grant State
t
20
t
21
CLK
STPCLK
NMI
SMI
A
STPCLK
Sampled
Note:
A = Earliest time at which NMI or SMI is recognized.
A RESET or SRESET brings the CPU from the Stop
Grant state to the Normal state. The CPU recognizes
the inputs required for cache invalidations (HOLD,
AHOLD, BOFF, and EADS) as explained later. The CPU
does not recognize any other inputs while in the Stop
Grant state. Input signals to the
CPU are not recognized
until 1 clock after STPCLK is deasserted (see Figure 21).
While in the Stop Grant state, the CPU does not recog-
nize transitions on the interrupt signals (SMI, NMI, and
INTR). Driving an active edge on either SMI or NMI does
not guarantee recognition and service of the interrupt
request following exit from the Stop Grant state. How-
ever, if one of the interrupt signals (SMI, NMI, or INTR)
is driven active while the CPU is in the Stop Grant state,
and held active for at least one CLK after STPCLK is
deasserted, the corresponding interrupt will be serviced.
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