參數(shù)資料
型號(hào)： AM5X86
廠商： Advanced Micro Devices, Inc.
英文描述： High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能單片32位微處理器)
中文描述： 高性能設(shè)計(jì)的片上集成完整的32位架構(gòu)Micrprocessor（高性能單片32位微處理器）
文件頁(yè)數(shù)： 27/67頁(yè)
文件大?。?/td> 1201K
代理商： AM5X86
Am5
X
86 Microprocessor
27
AMD
PRELIMINARY
Step 1 HOLD places the microprocessor in Snooping
mode. HLDA must be High for a minimum of
one clock cycle before EADS assertion. In the
fastest case, this means that HOLD asserts one
clock cycle before the HLDA response.
Step 2 EADS and INV are asserted. If INV is 0, snoop-
ing is caused by a read access. If INV is 1,
snooping is caused by a write access. EADS is
not sampled again until after the modified line
is written back to memory. It is detected again
as early as in Step 11.
Step 3 Two clock cycles after EADS is asserted, HITM
becomes valid, and is 0 because the line is
modified.
Step 4 In the next clock the core system logic deasserts
the HOLD signal in response to the HITM = 0.
The core system logic backs off the current bus
master at the same time so that the micropro-
cessor can access the bus. HOLD can be re-
asserted immediately after ADS is asserted for
burst cycles.
Step 5 The snooping cache starts its write-back of the
modified line by asserting ADS = 0, CACHE = 0,
and W/R = 1. The write access is a burst write.
The number of clock cycles between deassert-
ing HOLD to the snooping cache and first as-
serting ADS for the write-back cycles can vary.
In this example, it is one clock cycle, which is
the shortest possible time. Regardless of the
number of clock cycles, the start of the write-
back is seen by ADS going Low.
Step 6 The write-back access is finished when BLAST
and BRDY both are 0.
Step 7 In the clock cycle after the final write-back ac-
cess, the processor drives HITM back to 1.
Step 8 HOLD is sampled by the microprocessor.
Step 9 A minimum of 1 clock cycle after the completion
of the pending access, HLDA transitions to 1,
acknowledging the HOLD request.
Step 10The core system logic removes hold-off control
to the external bus master. This allows the ex-
ternal bus master to immediately retry the abort-
ed access. ADS is strobed Low, which
generates EADS Low in the same clock cycle.
Step 11The bus master restarts the aborted access.
EADS and INV are applied to the microproces-
sor as before. This starts another snoop cycle.
The status of the addressed line is now either shared
(INV = 0) or is changed to invalid (INV = 1).
4.8.5.1
HOLD/HLDA Write-Back Design
Considerations
When designing a write-back cache system that uses
HOLD/HLDA as the bus arbitration method, the follow-
ing considerations must be observed to ensure proper
operation (see Figure 10).
HLDA
CLK
ADS
BLAST
BRDY
HOLD
Valid Hold Assertion
Figure 10. Valid HOLD Assertion During Write-Back
HITM
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