參數(shù)資料
型號(hào)： AM53C96KC
廠商： ADVANCED MICRO DEVICES INC
元件分類： 總線控制器
英文描述： High Performance SCSI Controller
中文描述： SCSI BUS CONTROLLER, PQFP100
封裝： 35 MM, CARRIER RING, PLASTIC, QFP-100
文件頁(yè)數(shù)： 28/63頁(yè)
文件大?。?/td> 455K
代理商： AM53C96KC
P R E L I M I N A R Y
AMD
28
Am53C94/Am53C96
Control Register One (08H) Read/Write
Control Register One
CNTLREG1
Address: 08
H
Type: Read/Write
7
6
5
4
3
2
1
0
ETM
DISR
PTE
PERE
STE
CID2
CID1
CID0
0
0
0
0
0
x
x
x
Disable Interrupt on SCSI Reset
Extended Timing Mode
Parity Test Enable
Parity Error Reporting Enable
Self Test Enable
Chip ID 2:0
16506C-28
The Control Register 1 (CNTLREG1) sets up the device
with various operating parameters.
CNTLREG1 – Bit 7 – ETM – Extended Timing Mode
The ETM bit is set if an extra clock period is required be-
tween the data being driven on the bus and the
REQ
or
ACK
being asserted. This is some times necessary in
high capacitive loading environments. The ETM bit is re-
set to zero by a hard or soft reset.
CNTLREG1 – Bit 6 – DISR – Disable Interrupt on
SCSI Reset
The DISR bit masks the reporting of the SCSI reset.
When the DISR bit is set and a SCSI reset is asserted,
the device will disconnect from the SCSI bus and remain
idle without interrupting the host processor. When the
DISR bit is reset and a SCSI reset is asserted the device
will respond by interrupting the host processor. The
DISR bit is reset to zero by a hard or soft reset.
CNTLREG1 – Bit 5 – PTE – Parity Test Enable
The PTE bit is for test use only. When the PTE bit is set
the parity on the output (SCSI or host processor) bus is
forced to the value of the MSB (bit 7) of the output data
from the internal FIFO. This allows parity errors to be
created to test the hardware and software. The PTE bit
is reset to zero by a hard or soft reset.
CNTLREG1 – Bit 4 – PERE – Parity Error Report-
ing Enable
The PERE bit enables the checking and reporting of par-
ity errors on incoming SCSI bytes during the information
transfer phase. When the PERE bit set and a bad parity
is detected, the PE bit in the STATREG is will be set but
an interrupt will not be generated. In the initiator mode
the
ATN
signal will also be asserted on the SCSI bus.
When the PERE bit is reset and a bad parity occurs it is
not detected and no action is taken.
CNTLREG1 – Bit 3 – STE – Self Test Enable
The STE bit is for test use only. When the STE bit is set
the device is placed in a test mode which enables the
device to access the test register at address 0AH. To re-
set this bit and to resume normal operation the device
must be issued a hard or soft reset.
CNTLREG1 – Bit 2:0 – CID 2:0 – Chip ID 2:0
The Chip ID 2:0 bits specify the binary coded value of
the device ID on the SCSI bus. The device will arbitrate
with this ID and will respond to selection or reselection to
this ID. At power-up the state of these bit are undefined.
These bits are not affected by hard or soft reset.
相關(guān)PDF資料
PDF描述
AM53C96KCW High Performance SCSI Controller
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AM80C286 Circular Connector; No. of Contacts:10; Series:MS27508; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle RoHS Compliant: No
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