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參數(shù)資料
| 型號： | AM53C96KC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 總線控制器 |
| 英文描述： | High Performance SCSI Controller |
| 中文描述： | SCSI BUS CONTROLLER, PQFP100 |
| 封裝： | 35 MM, CARRIER RING, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 19/63頁 |
| 文件大?。?/td> | 455K |
| 代理商： | AM53C96KC |
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P R E L I M I N A R Y
AMD
19
Am53C94/Am53C96
Status Register (04H) Read
Status Register
STATREG
Address: 04
H
Type: Read
7
6
5
4
3
2
1
0
INT
IOE
PE
CTZ
GCV
MSG
C/D
I/O
0
0
0
0
0
x
x
x
Illegal Operation Error
Interrupt
Parity Error
Count to Zero
Group Code Valid
Message
Command/Data
Input/Output
16506C-20
This read only register contains flags to indicate the
status and phase of the SCSI transactions. It indicates
whether an interrupt or error condition exists. It should
be read every time the host is interrupted to determine
which device is asserting an interrupt. The data is
latched until the Interrupt Status Register is read. The
phase bits will be latched only if latching is enabled in the
Control Register 2, otherwise, it will indicate the current
SCSI phase. If command stacking is used, two inter-
rupts might occur. Reading this register will clear the
status information for the first interrupt and update the
Status Register for the second interrupt.
STATREG – Bit 7 – INT – Interrupt
The INT bit is set when the device asserts the interrupt
output. This bit will be cleared by a hardware or software
reset. Reading the Interrupt Status Register will deas-
sert the interrupt output and also clear this bit.
STATREG – Bit 6 – IOE – Illegal Operation Error
The IOE bit is set when an illegal operation is attempted.
This condition will not cause an interrupt, it will be de-
tected by reading the status register while servicing an-
other interrupt. The following conditions will cause the
IOE bit to be set:
I
DMA and SCSI transfer directions are opposite.
FIFO overflows.
In initiator mode an unexpected phase change
detected during synchronous data transfer.
Command Register overwritten.
This bit will be cleared by reading the Interrupt Status
Register or by a hard or soft reset.
I
I
I
STATREG – Bit 5 – PE – Parity Error
The PE bit is set if the parity checking option is enabled
in Control Register 1 and the device detects a parity er-
ror on incoming SCSI data, command, status or mes-
sage bytes. Detection of a parity error condition will not
cause an interrupt but will be reported with other inter-
rupt causing conditions. When a parity error is detected
in the information phase of the initiator mode
ATN
is as-
serted on the SCSI bus.
This bit will be cleared by reading the Interrupt Status
Register or by a hard or soft reset.
STATREG – Bit 4 – CTZ – Count To Zero
The CTZ bit is set when the Current Transfer Count
Register (CTCREG) has counted down to zero. This bit
will be reset when the CTCREG is written.
Reading the Interrupt Status Register will not affect this
bit. This bit will however be cleared by a hard or soft re-
set.
Note:
A non-DMA NOP will not reset the CTZ bit since it does
not load the CTCREG but a DMA NOP will reset this bit
since it loads the CTCREG.
STATREG – Bit 3 – GCV – Group Code Valid
The GCV bit is set if the group code field in the Com-
mand Descriptor Block (CDB) is one that is defined by
the ANSI Committee in their document X3.131 – 1986. If
the SCSI-2 Feature Enable (S2FE) bit in the Control
Register 2 (CNTLREG2) is set, Group 2 commands will
be treated as ten byte commands and the GCV bit will be
set. If S2FE is reset then Group 2 commands will be
treated as reserved commands. Group 3 and 4 com-
mand will always be considered as reserved com-
mands. The device will treat all reserved commands as
six byte commands. Group 6 commands will always be
treated as vendor unique six byte commands and Group
7 commands will always be treated as vendor unique
ten byte commands.
The GCV bit is cleared by reading the Interrupt Status
Register (INSTREG) or by a hard or soft reset.
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PDF描述 |
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| AM80C186 | Circular Connector; No. of Contacts:3; Series:MS27508; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:12-3 RoHS Compliant: No |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM53C96KCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High Performance SCSI Controller |
| AM53C974KC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SCSI Bus Interface/Controller |
| AM53CF94 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Enhanced SCSI-2 Controller (ESC) |
| AM53CF94/AM53CF96 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am53CF94/Am53CF96 ? 572KB (PDF) Enhanced SCSI-2 Controller (ESC)? |
| AM53CF94JC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Enhanced SCSI-2 Controller (ESC) |
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