參數(shù)資料
型號(hào): AM53C96KC
廠商: ADVANCED MICRO DEVICES INC
元件分類(lèi): 總線控制器
英文描述: High Performance SCSI Controller
中文描述: SCSI BUS CONTROLLER, PQFP100
封裝: 35 MM, CARRIER RING, PLASTIC, QFP-100
文件頁(yè)數(shù): 20/63頁(yè)
文件大?。?/td> 455K
代理商: AM53C96KC
P R E L I M I N A R Y
AMD
20
Am53C94/Am53C96
STATREG – Bit 2 – MSG – Message
STATREG – Bit 1 – C/D – Command/Data
STATREG – Bit 0 – I/O – Input/Output
Bit2
MSG
Bit1
C/D
Bit0
I/O
SCSI Phase
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Message In
Message Out
Reserved
Reserved
Status
Command
Data_In
Data_Out
The MSG, C/D and I/O bits together can be referred to
as the SCSI Phase bits. They indicate the phase of the
SCSI bus. These bits may be latched or unlatched de-
pending on the option selected in Control Register 2
(CNTLREG2) by the Latch SCSI Phase (LSP) bit.
In the latched mode the SCSI phase bits are latched at
the end of a command and the latch is opened when the
Interrupt Status Register (INSTREG) is read. In the un-
latched mode, they indicate the phase of the SCSI bus
when this register is read.
SCSI Destination ID Register (04H) Write
RES
RES
RES
RES
RES
0
0
0
0
0
SCSI Destination ID Register
SDIDREG
Address: 04
H
Type: Write
7
6
5
4
3
2
1
0
DID2
DID1
DID0
x
x
x
Reserved
Reserved
Reserved
Reserved
Reserved
SCSI Destination ID 2:0
16506C-21
SDIDREG – Bits 7:3 – RES – Reserved
SDIDREG – Bits 2:0 – DID 2:0 – Destination ID 2:0
The DID 2:0 bits are the encoded SCSI ID of the device
on the SCSI bus which needs to be selected or
reselected.
DID2
DID1
DID0
SCSI ID
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
7
6
5
4
3
2
1
0
At power-up the state of these bits is undefined. The DID 2:0
bits are not affected by reset.
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