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| 型號： | AM50DL128BG |
| 英文描述： | Am50DL128BG - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| 中文描述： | Am50DL128BG -堆疊式多芯片封裝（MCP）閃存和SRAM |
| 文件頁數(shù)： | 63/70頁 |
| 文件大?。?/td> | 1042K |
| 代理商： | AM50DL128BG |
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62
Am50DL9608G
May 19, 2003
P R E L I M I N A R Y
PSEUDO SRAM AC CHARACTERISTICS
Write Cycle
Notes:
1. WE# controlled.
2. t
CW
is measured from CE1#s going low to the end of write.
3. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CE1#s or WE# going high.
4. t
AS
is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (t
WP
) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
WP
is measured from the beginning of write
to the end of write.
Figure 30.
Pseudo SRAM Write Cycle—WE# Control
Parameter
Symbol
Description
Speed
Unit
55
70
t
WC
Write Cycle Time
Min
55
70
ns
t
Cw
Chip Enable to End of Write
Min
45
55
ns
t
AS
Address Setup Time
Min
0
ns
t
AW
Address Valid to End of Write
Min
45
55
ns
t
BW
UB#s, LB#s to End of Write
Min
45
55
ns
t
WP
Write Pulse Time
Min
45
55
ns
t
WR
Write Recovery Time
Min
0
ns
t
WHZ
Write to Output High-Z
Min
0
ns
Max
25
t
DW
Data to Write Time Overlap
Min
40
ns
t
DH
Data Hold from Write Time
Min
0
ns
t
OW
End Write to Output Low-Z
Min
5
ns
Address
CE1#s
Data Undefined
WE#
Data In
Data Out
t
WC
t
CW
(See Note 1)
t
AW
High-Z
High-Z
Data Valid
CE2s
t
CW
(See Note 1)
t
WP
(See Note 4)
t
AS
(See Note 3)
t
WR
t
DW
t
DH
t
OW
t
WHZ
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