參數(shù)資料
型號(hào)： AM50DL128BG
英文描述： Am50DL128BG - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述： Am50DL128BG -堆疊式多芯片封裝（MCP）閃存和SRAM
文件頁(yè)數(shù)： 59/70頁(yè)
文件大?。?/td> 1042K
代理商： AM50DL128BG
58
Am50DL9608G
May 19, 2003
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Alternate CE#f Controlled Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
Parameter
All Speed
Options
JEDEC
Std
Description
Unit
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
70
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
ELAX
t
AH
Address Hold Time
Min
40
ns
t
DVEH
t
DS
Data Setup Time
Min
40
ns
t
EHDX
t
DH
Data Hold Time
Min
0
ns
t
GHEL
t
GHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
WLEL
t
WS
WE# Setup Time
Min
0
ns
t
EHWH
t
WH
WE# Hold Time
Min
0
ns
t
ELEH
t
CP
CE#f Pulse Width
Min
40
ns
t
EHEL
t
CPH
CE#f Pulse Width High
Min
30
ns
t
WHWH1
t
WHWH1
Programming Operation
(Note 2)
Typ
7
μs
t
WHWH1
t
WHWH1
Accelerated Programming Operation,
Word or Byte (Note 2)
Typ
4
μs
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
0.4
sec
相關(guān)PDF資料
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