參數(shù)資料
型號(hào)： AM486DX
英文描述： Am486DX - Am486DX Block Diagram
中文描述： Am486DX - Am486DX框圖
文件頁(yè)數(shù)： 34/52頁(yè)
文件大?。?/td> 1242K
代理商： AM486DX
34
Am486DE2 Microprocessor
To account for these two situations, the system designer
must ensure that A20M is deasserted on entry to SMM.
A20M must be driven inactive before the first cycle of
the SMM state save, and must be returned to its original
level after the last cycle of the SMM state restore. This
can be done by blocking the assertion of A20M when
SMIACT is active.
CPU Reset During SMM
The system designer should take into account the fol-
lowing restrictions while implementing the CPU Reset
logic:
I
When running software written for the 80286 CPU,
a CPU RESET switches the CPU from Protected
mode to Real mode. RESET and SRESET have a
higher priority than SMI. When the CPU is in SMM,
the SRESET to the CPU during SMM should be
blocked until the CPU exits SMM. SRESET must be
blocked beginning from the time when SMI is driven
active. Care should be taken not to block the global
system RESET, which may be necessary to recover
from a system crash.
I
During execution of the RSM instruction to exit SMM,
there is a small time window between the
deassertion of SMIACT and the completion of the
RSM microcode. If a Protected mode to Real mode
SRESET is asserted during this window, it is possible
that the SMRAM space will be violated. The system
designer must guarantee that SRESET is blocked
until at least 20 CPU clock cycles after SMIACT has
been driven inactive or until the start of a bus cycle.
I
Any request for a CPU RESET for the purpose of
switching the CPU from Protected mode to Real
mode must be acknowledged after the CPU has
exited SMM. To maintain software transparency, the
system logic must latch any SRESET signals that
are blocked during SMM.
For these reasons, the SRESET signal should be used
for any soft resets, and the RESET signal should be
used for all
hard resets.
SMM and Second-Level Write Buffers
Before the processor enters SMM, it empties its internal
write buffers. This is to ensure that the data in the write
buffers is written to normal memory space, not SMM
space. When the CPU is ready to begin writing an SMM
state save to SMRAM, it asserts SMIACT. SMIACT may
be driven active by the CPU before the system memory
controller has had an opportunity to empty the second-
level write buffers.
To prevent the data from these second-level write buff-
ers from being written to the wrong location, the system
memory controller needs to direct the memory write cy-
cles to either SMM space or normal memory space. This
can be accomplished by saving the status of SMIACT
with the address for each word in the write buffers.
Nested SMI and I/O Restart
Special care must be taken when executing an SMI han-
dler for the purpose of restarting an l/O instruction. When
the CPU executes a Resume (RSM) instruction with the
l/O restart slot set, the restored EIP is modified to point
to the instruction immediately preceding the SMI re-
quest, so that the l/O instruction can be reexecuted. If a
new SMI request is received while the CPU is executing
an SMI handler, the CPU services this SMI request be-
fore restarting the original I/O instruction. If the I/O re-
start slot is set when the CPU executes the RSM
instruction for the second SMI handler, the RSM micro-
code decrements the restored EIP again. EIP then
points to an address different from the originally inter-
rupted instruction, and the CPU begins execution at an
incorrect entry point. To prevent this from occurring, the
SMI handler routine must not set the I/O restart slot dur-
ing the second of two consecutive SMI handlers.
SMM Software Considerations
SMM Code Considerations
The default operand size and the default address size
are 16 bits; however, operand-size override and ad-
dress-size override prefixes can be used as needed to
directly access data anywhere within the 4-Gbyte logical
address space.
With operand-size override prefixes, the SMI handler
can use jumps, calls and returns to transfer a control to
any location within the 4-Gbyte space. Note, however,
the following restrictions:
I
Any control transfer that does not have an operand-
size override prefix truncates EIP to 16 Low-order
bits.
I
Due to the Real mode style of base-address
formation, a long jump or call cannot transfer control
segment with a base address of more than 20 bits
(1 Mbyte).
Exception Handling
Upon entry into SMM, external interrupts that require
handlers are disabled (the IF in EFLAGS is cleared).
This is necessary because, while the processor is in
SMM, it is running in a separate memory space. Con-
sequently, the vectors stored in the interrupt descriptor
table (IDT) for the prior mode are not applicable. Before
allowing exception handling (or software interrupts), the
SMM program must initialize new interrupt and excep-
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相關(guān)代理商/技術(shù)參數(shù)
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AM486DX/DX2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am486DX/DX2 Hardware Reference Manual
AM486DX2 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am5X86⑩ Microprocessor Family
AM486DX2-66V16BGC 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 168-Pin PGA
AM486DX2-66V16BGI 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 168-Pin PGA
AM486DX2-66V16BHI 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 208-Pin SQFP
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