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參數(shù)資料
| 型號： | AM486DX |
| 英文描述： | Am486DX - Am486DX Block Diagram |
| 中文描述： | Am486DX - Am486DX框圖 |
| 文件頁數(shù)： | 22/52頁 |
| 文件大?。?/td> | 1242K |
| 代理商： | AM486DX |
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22
Am486DE2 Microprocessor
SYSTEM MANAGEMENT MODE
Overview
The Am486DE2 microprocessor supports four modes:
Real, Virtual, Protected, and System Management
Mode (SMM).
As an operating mode, SMM has a distinct
processor environment, interface, and hardware/soft-
ware features. SMM lets the system designer add new
software-controlled features to the computer products
that always operate transparent to the operating system
(OS) and software applications. SMM is intended for use
only by system firmware, not by applications software
or general-purpose systems software.
The SMM architectural extension consists of the follow-
ing elements:
1. System Management Interrupt (SMI) hardware
interface
2. Dedicated and secure memory space (SMRAM) for
SMI handler code and CPU state (context) data with
a status signal for the system to decode access to
that memory space, SMIACT
3. Resume (RSM) instruction, for exiting SMM
4. Special features, such as I/O Restart and I/O
instruction information, for transparent power
management of I/O peripherals, and Auto Halt
Restart
Terminology
The following terms are used throughout the discussion
of System Management Mode.
I
SMM:
System Management Mode. This is the
operating environment that the processor (system)
enters when servicing a System Management
Interrupt.
I
SMI:
System Management Interrupt. This is the
trigger mechanism for the SMM interface. When SMI
is asserted (SMI pin asserted Low), it causes the
processor to invoke SMM. The SMI pin is the only
means of entering SMM.
I
SMI handler:
System Management Mode handler.
This is the code that is executed when the processor
is in SMM. An example application that this code
might implement is a power-management-control or
a system-control function.
I
RSM:
Resume instruction. This instruction is used
by the SMI handler to exit the SMM and return to the
interrupted OS or application process.
I
SMRAM:
This is the physical memory dedicated to
SMM. The SMI handler code and related data reside
in this memory. The processor also uses this
memory to store its context before executing the SMI
handler. The operating system and applications
should not have access to this memory space.
I
SMBASE:
This is a control register that contains the
base address that defines the SMRAM space.
I
Context:
This term refers to the processor state. The
SMM discussion refers to the context, or processor
state, just before the processor invokes SMM. The
context normally consists of the CPU registers that
fully represent the processor state.
I
Context Switch:
A context switch is the process of
either saving or restoring the context. The SMM
discussion refers to the context switch as the process
of saving/restoring the context while invoking/exiting
SMM, respectively.
I
SMSAVE:
A mechanism that saves and restores all
internal registers to and from SMRAM.
System Management Interrupt Processing
The system interrupts the normal program execution
and invokes SMM by generating a System Management
Interrupt (SMI) to the CPU. The CPU services the SMI
by executing the following sequence (see Figure 4).
1. The CPU asserts the SMIACT signal, instructing the
system to enable the SMRAM.
2. The CPU saves its state (internal register) to
SMRAM. It starts at the SMBASE relative address
location (see “SMRAM” on page 24), and proceeds
downward in a stack-like fashion.
3. The CPU switches to the SMM processor
environment (an external pseudo-Real mode).
4. The CPU then jumps to the absolute address of
SMBASE + 8000h in SMRAM to execute the SMI
handler. This SMI handler performs the system
management activities.
Note:
If the SMRAM shares the same physical address
location with part of the system RAM, it is “overlaid”
SMRAM. To preserved cache consistency and correct
SMM operation in systems using overlaid SMRAM, the
cache must be flushed via the FLUSH pin when entering
SMM.
5. The SMI handler then executes the RSM instruction,
which restores the CPU’s context from SMRAM,
deasserts the SMIACT signal, and then returns
control to the previously interrupted program
execution.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AM486DX/DX2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am486DX/DX2 Hardware Reference Manual |
| AM486DX2 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am5X86⑩ Microprocessor Family |
| AM486DX2-66V16BGC | 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 168-Pin PGA |
| AM486DX2-66V16BGI | 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 168-Pin PGA |
| AM486DX2-66V16BHI | 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 208-Pin SQFP |
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