- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362278 > AM486DX Am486DX - Am486DX Block Diagram PDF資料下載
參數(shù)資料
| 型號： | AM486DX |
| 英文描述： | Am486DX - Am486DX Block Diagram |
| 中文描述： | Am486DX - Am486DX框圖 |
| 文件頁數(shù)： | 27/52頁 |
| 文件大?。?/td> | 1242K |
| 代理商： | AM486DX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
Am486DE2 Microprocessor
27
I
The only way to enter SMM is via a type of
nonmaskable interrupt triggered by an external
signal.
I
The processor begins executing SMM code from a
separate address space, referred to earlier as
system management RAM (SMRAM).
I
Upon entry into SMM, the processor saves the
register state of the interrupted program (depending
on the save mode) in a part of SMRAM called the
SMM context save space.
I
All interrupts normally handled by the operating
system or applications are disabled upon SMM entry.
I
A special instruction, RSM, restores processor
registers from the SMM context save space and
returns control to the interrupted program.
Similar to Real mode, SMM has no privilege levels or
address mapping. SMM programs can execute all I/O
and other system instructions and can address up to 4
Gbyte of memory.
Exiting System Management Mode
The RSM instruction (opcode 0F AAh) leaves SMM and
returns control to the interrupted program. The RSM in-
struction can be executed only in SMM. An attempt to
execute the RSM instruction outside of SMM generates
an invalid opcode exception. When the RSM instruction
is executed and the processor detects invalid state in-
formation during the reloading of the save state, the pro-
cessor enters the shutdown state. This occurs in the
following situations:
I
The value in the State Dump base field is not a
32-Kbyte aligned address.
I
A combination of bits in CR0 is illegal: PG=1 and
PE=0, or NW=1 and CD=0.
In shutdown mode, the processor stops executing in-
structions until an NMI interrupt is received or reset ini-
tialization is invoked. The processor generates a
shutdown bus cycle.
Three SMM features can be enabled by writing to control
slots in the SMRAM state save area:
1.
Auto
Halt Restart
. It is possible for the SMI request
to interrupt the HALT state. The SMI handler can tell
the RSM instruction to return control to the HALT
instruction or to return control to the instruction
following the HALT instruction by appropriately
setting the Auto Halt Restart slot. The default
operation is to restart the HALT instruction.
2.
I/O Trap Restart
. If the SMI was generated on an I/O
access to a powered-down device, the SMI handler
can instruct the RSM instruction to re-execute that I/O
instruction by setting the I/O Trap Restart slot.
3.
SMBASE Relocation
. The system can relocate the
SMRAM by setting the SMBASE Relocation slot in
the state save area. The RSM instruction sets
SMBASE in the processor based on the value in the
SMBASE relocation slot. The SMBASE must be
aligned on 32-Kbyte boundaries.
A RESET also causes execution to exit from SMM.
Processor Environment
When an SMI signal is recognized on an instruction ex-
ecution boundary, the processor waits for all stores to
complete, including emptying the write buffers. The final
write cycle is complete when the system returns RDY
or BRDY. The processor then drives SMIACT active,
saves its register state to SMRAM space, and begins to
execute the SMI handler.
SMI has greater priority than debug exceptions and ex-
ternal interrupts. This means that if more than one of
these conditions occur at an instruction boundary, only
the SMI processing occurs. Subsequent SMI requests
are not acknowledged while the processor is in SMM.
The first SMI request that occurs while the processor is
in SMM is latched, and serviced when the processor
exits SMM with the RSM instruction. Only one SMI signal
is latched by the CPU while it is in SMM. When the CPU
invokes SMM, the CPU core registers are initialized as
indicated in Table 4.
Figure 9. Transition to and from SMM
Virtual
Mode
System
Management
Mode
Reset
Reset
or
RSM
SMI
RSM
RSM
VM=1
PE=1
Reset
or
PE=0
VM=0
Real
Mode
Protected
Mode
SMI
SMI
相關PDF資料 |
PDF描述 |
|---|---|
| AM486DXPGA | Am486DX PGA - Am486DX PGA Package Temperature Comparisons |
| AM486DXSQFP | 70NS, PLCC, IND TEMP(EEPROM) |
| AM486 | Am486 Microprocessor Software User＇s Manual? 4.40MB (PDF) |
| AM49DL3208G | Am49DL3208G - Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM |
| AM49DL320BG | Am49DL320BG - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM486DX/DX2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am486DX/DX2 Hardware Reference Manual |
| AM486DX2 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am5X86⑩ Microprocessor Family |
| AM486DX2-66V16BGC | 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 168-Pin PGA |
| AM486DX2-66V16BGI | 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 168-Pin PGA |
| AM486DX2-66V16BHI | 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 208-Pin SQFP |
發(fā)布緊急采購，3分鐘左右您將得到回復。