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參數(shù)資料
| 型號(hào)： | AM486DX |
| 英文描述： | Am486DX - Am486DX Block Diagram |
| 中文描述： | Am486DX - Am486DX框圖 |
| 文件頁數(shù)： | 17/52頁 |
| 文件大?。?/td> | 1242K |
| 代理商： | AM486DX |
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Am486DE2 Microprocessor
17
FUNCTIONAL DESCRIPTION
Note:
This Am486DE microprocessor does not support
Write-back mode. If you are designing n a shared-mem-
ory system or using cache coherency (including snoop-
ing and locked accesses), use one of the Am486DE
products that supports write back.
Overview
The Am486DE2 microprocessor uses a 32-bit architec-
ture with on-chip memory management and cache
memory units. The instruction set includes the complete
486 microprocessor instruction set, along with exten-
sions to serve the new extended applications. All soft-
ware written for the 486 microprocessor and previous
members of the x86 architectural family can run on the
Am486DE2 microprocessor without modification.
The on-chip Memory Management Unit (MMU) is com-
pletely compatible with the 486 MMU. The MMU in-
cludes a segmentation unit and a paging unit.
Segmentation allows management of the logical ad-
dress space by providing easy data and code relocat-
ability and efficient sharing of global resources. The
paging mechanism operates beneath segmentation and
is transparent to the segmentation process. Paging is
optional and can be disabled by system software. Each
segment can be divided into one or more 4-Kbyte seg-
ments. To implement a virtual memory system, the
Am486DE2 microprocessor supports full restartability
for all page and segment faults.
Memory
Memory is organized into one or more variable length
segments, each up to 4 Gbyte (2
32
bytes). A segment
can have attributes associated with it, including its loca-
tion, size, type (e.g., stack, code, or data), and protection
characteristics. Each task on a microprocessor can
have a maximum of 16,381 segments, each up to
4 Gbyte. Thus, each task has a maximum of 64 Tbyte
of virtual memory.
The segmentation unit provides four levels of protection
for isolating and protecting applications and the operat-
ing system from each other. The hardware-enforced
protection allows high-integrity system designs.
Modes of Operation
The Am486DE2 microprocessor has four modes of op-
eration: Real Address mode (Real mode), Virtual 8086
Address mode (Virtual mode), Protected Address mode
(Protected mode), and System Management mode
(SMM).
Real Mode
In Real mode, the Am486DE2 microprocessor operates
as a fast 8086. Real mode is required primarily to set up
the processor for Protected mode operation.
Virtual Mode
In Virtual mode, the processor appears to be in Real
mode, but can use the extended memory accessing of
Protected mode.
Protected Mode
Protected mode provides access to the sophisticated
memory management paging and privilege capabilities
of the processor.
System Management Mode
SMM is a special operating mode described in detail in
“System Management Mode” on page 22.
Write-Through Cache Architecture
The Am486DE2 microprocessor supports the standard
486DX-type write-through cache architecture, which is
characterized by the following:
I
External read accesses are placed in the cache if
they meet proper caching requirements.
I
Subsequent reads to the data in the cache are made
if the address is stored in the cache tag array.
I
Write operations to a valid address in the cache are
updated in the cache andto external memory. This
data writing technique is called write-through
The write-through cache implementation forces all
writes to flow through to the external bus and back to
main memory. Consequently, the write-through cache
generates a large amount of bus traffic on the external
data bus.
Cache Replacement Description
The cache-line-replacement algorithm uses the stan-
dard Am486 CPU pseudo LRU (least recently used)
strategy. When a line must be placed in the internal
cache, the microprocessor first checks to see if there is
an invalid line available in the set. If no invalid line is
available, the LRU algorithm replaces the least-recently
used cache line in the four-way set with the new cache
line. If the cache line for replacement is modified, the
modified cache line is placed into the copy-back buffer
for copying back to external memory, and the new cache
line is placed into the cache. This copy-back ensures
that the external memory is updated with the modified
data upon replacement.
Memory Configuration
In computer systems, memory regions require specific
caching and memory write methods. For example, some
memory regions are noncacheable while others are
cacheable but are write-through. To allow maximum
memory configuration, the microprocessor supports
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| AM486DXPGA | Am486DX PGA - Am486DX PGA Package Temperature Comparisons |
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| AM486 | Am486 Microprocessor Software User＇s Manual? 4.40MB (PDF) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM486DX/DX2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am486DX/DX2 Hardware Reference Manual |
| AM486DX2 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am5X86⑩ Microprocessor Family |
| AM486DX2-66V16BGC | 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 168-Pin PGA |
| AM486DX2-66V16BGI | 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 168-Pin PGA |
| AM486DX2-66V16BHI | 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 208-Pin SQFP |
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