參數(shù)資料
型號： AM486DE2
英文描述： Am486DE2 Microprocessor Data Sheet
中文描述： Am486DE2微處理器數(shù)據(jù)表
文件頁數(shù)： 26/52頁
文件大?。?/td> 1242K
代理商： AM486DE2
26
Am486DE2 Microprocessor
the SMI handler, with the changed values restored to
the processor register by the RSM instruction. Some
register images are read-only, and must not be modified.
(Modifying these registers results in unpredictable be-
havior.) The values stored in the reservedareas may
change in future CPUs. An SMI handler should not rely
on values stored in a reserved area.
The following registers are written out during SMSAVE
mode to the RESERVED memory locations (7FA7h–
7F98h, 7F93h–7F8Ch, and 7F87h–7F08h), but are not
visible to the system software programmer:
I
DR3–DR0
I
CR2
I
CS, DS, ES, FS, GS, and SS hidden descriptor
registers
I
EIP_Previous
I
GDT Attributes and Limits
I
IDT Attributes and Limits
I
LDT Attributes, Base, and Limits
I
TSS Attributes, Base, and Limits
If an SMI request is issued to power down the CPU, the
values of all reserved locations in the SMM state save
must be saved to nonvolatile memory.
The following registers are not automatically saved and
restored by SMI and RSM:
I
TR7–TR3
I
FPU registers:
— STn
— FCS
— FSW
— Tag Word
— FP instruction pointer
— FP opcode
— Operand pointer
Note:
You can save the FPU state by using an FSAVE
or FNSAVE instruction.
For all SMI requests except for power-down suspend/
resume, these registers do not have to be saved be-
cause their contents will not change. During a power-
down suspend/resume, however, a resume reset clears
these registers back to their default values. In this case,
the suspend SMI handler should read these registers
directly to save them and restore them during the power-
up resume. Anytime the SMI handler changes these reg-
isters in the CPU, it must also save and restore them.
Entering System Management Mode
SMM is one of the major operating modes, along with
Protected mode, Real mode, and Virtual mode. Figure
9 shows how the processor can enter SMM from any of
the three modes and then return.
The external signal SMI causes the processor to switch
to SMM. The RSM instruction exits SMM. SMM is trans-
parent to applications programs and operating systems
for the following reasons:
Table 3. SMRAM State Save Map
Register
Offset*
7FFCh
CRO
7FF8h
CR3
7FF4h
EFLAGS
7FF0h
EIP
7FECh
EDI
7FE8h
ESI
7FE4h
EBP
7FE0h
ESP
7FDCh
EBX
7FD8h
EDX
7FD4h
ECX
7FD0h
EAX
7FCCh
DR6
7FC8h
DR7
7FC4h
TR*
7FC0h
LDTR*
7FBCh
GS*
7FB8h
FS*
7FB4h
DS*
7FB0h
SS*
7FACh
CS*
7FA8h
ES*
7FA7h–7F98h Reserved
7F94h
IDT Base
7F93h–7F8Ch Reserved
7F88h
GDT Base
7F87h–7F08h
Reserved
7F04h
I/O Trap Word
7F02h
Auto Halt Restart
7F00h
I/O Trap Restart
7EFCh
SMM Revision Identifier
7EF8h
State Dump Base
7EF7h–7E00h Reserved
Note:
*Upper 2 bytes are not modified.
Register
Writable
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
No
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