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| 型號(hào)： | AM486DE2 |
| 英文描述： | Am486DE2 Microprocessor Data Sheet |
| 中文描述： | Am486DE2微處理器數(shù)據(jù)表 |
| 文件頁數(shù)： | 20/52頁 |
| 文件大小： | 1242K |
| 代理商： | AM486DE2 |
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20
Am486DE2 Microprocessor
Clock Control State Diagram
Figure 2 shows the state transitions during a Stop Clock
cycle.
Normal State
This is the normal operating state of the CPU. While in
the normal state, the CLK input can be dynamically
changed within the specified CLK period stability limits.
Stop Grant State
The Stop Grant state provides a low-power state that
can be entered by simply asserting the external
STPCLK interrupt pin. When the Stop Grant bus cycle
has been placed on the bus, and either RDY or BRDY
is returned, the CPU is in this state. The CPU returns to
the normal execution state 10–20 clock periods after
STPCLK has been deasserted.
While in the Stop Grant state, the pull-up resistors on
STPCLK and UP are disabled internally. The system
must continue to drive these inputs to the state they were
in immediately before the CPU entered the Stop Grant
state. For minimum CPU power consumption, all other
input pins should be driven to their inactive level while
the CPU is in the Stop Grant state.
A RESET or SRESET brings the CPU from the Stop
Grant state to the Normal state. The CPU recognizes
the inputs required for cache invalidations (HOLD,
AHOLD, BOFF, and EADS), as explained later. The
CPU does not recognize any other inputs while in the
Stop Grant state. Input signals to the
CPU are not rec-
ognized until 1 clock after STPCLK is deasserted (see
Figure 3).
While in the Stop Grant state, the CPU does not recog-
nize transitions on the interrupt signals (SMI, NMI, and
INTR). Driving an active edge on either SMI or NMI does
not guarantee recognition and service of the interrupt
request following exit from the Stop Grant state.
However, if one of the interrupt signals (SMI, NMI or
INTR) is driven active while the CPU is in the Stop Grant
state, and held active for at least one CLK after STPCLK
is deasserted, the corresponding interrupt will be ser-
viced. The Am486DE2 processor requires INTR to be
held active until the CPU issues an interrupt acknowl-
edge cycle to guarantee recognition. This condition also
applies to the existing Am486 CPUs.
In the Stop Grant state, the system can stop or change
the CLK input. When the clock stops, the CPU enters
the Stop Clock state. The CPU returns to the Stop Grant
state immediately when the CLK input is restarted. You
must hold the STPCLK input Low until a stabilized fre-
quency has been maintained for at least 1 ms to ensure
that the PLL has had sufficient time to stabilize.
The CPU generates a Stop Grant bus cycle when en-
tering the state from the Normal or the Auto Halt Power-
Down state. When the CPU enters the Stop Grant state
from the Stop Clock state or the Stop Clock Snoop state,
the CPU does not generate a Stop Grant bus cycle.
Stop Clock State
Stop Clock state is entered from the Stop Grant state by
stopping the CLK input (either logic High or logic Low).
None of the CPU input signals should change state while
the CLK input is stopped. Any transition on an input
signal (except INTR) before the CPU has returned to the
Stop Grant state may result in unpredictable behavior.
If INTR goes active while the CLK input is stopped, and
stays active until the CPU issues an interrupt acknowl-
edge bus cycle, it is serviced in the normal manner. Sys-
tem design must ensure the CPU is in the correct state
prior to asserting cache invalidation or interrupt signals
to the CPU.
Auto Halt Power-Down State
A HALT instruction causes the CPU to enter the Auto
Halt Power-Down state. The CPU issues a normal HALT
bus cycle, and only transitions to the Normal state when
INTR, NMI, SMI, RESET, or SRESET occurs.
The system can generate a STPCLK while the CPU is
in the Auto Halt Power-Down state. The CPU generates
a Stop Grant bus cycle when it enters the Stop Grant
state from the HALT state. When the system deasserts
the STPCLK interrupt, the CPU returns execution to the
HALT state. The CPU generates a new HALT bus cycle
when it reenters the HALT state from the Stop Grant
state.
SRESET FUNCTION
The Am486DE2 microprocessor supports a soft reset
function through the SRESET pin. SRESET forces the
processor to begin execution in a known state. The pro-
cessor state after SRESET is the same as after RESET
except that the internal caches, CD and NW in CR0,
write buffers, SMBASE registers, and floating-point reg-
isters retain the values they had prior to SRESET, and
cache snooping is allowed. The processor starts execu-
tion at physical address FFFFFFF0h. SRESET can be
used to help performance for DOS extenders written for
the 80286 processor. SRESET provides a method to
switch from Protected to Real mode while maintaining
the internal caches, CR0, and the FPU state. SRESET
may not be used in place of RESET after power-up.
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