- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362278 > AM486DE2 Am486DE2 Microprocessor Data Sheet PDF資料下載
參數(shù)資料
| 型號： | AM486DE2 |
| 英文描述： | Am486DE2 Microprocessor Data Sheet |
| 中文描述： | Am486DE2微處理器數(shù)據(jù)表 |
| 文件頁數(shù)： | 42/52頁 |
| 文件大?。?/td> | 1242K |
| 代理商： | AM486DE2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁當前第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
42
Am486DE2 Microprocessor
Switching Characteristics for 33-MHz Bus (66-MHz Microprocessor)
V
CC
= 3.3 V ±0.3 V; T
CASE
= 0°C to + 85°C; C
L
= 50 pF unless otherwise specified
1
Symbol
Parameter
Min
8
30
Max
33
125
Unit
MHz
ns
Figure
Notes
Frequency
CLK Period
Note 2
t
1
39
t
1a
CLK Period Stability
0.1%
Adjacent Clocks
Notes 3 and 4
Note 3
Note 3
Note 3
Note 3
Note 5
t
2
t
3
t
4
t
5
CLK High Time at 2 V
CLK Low Time at 0.8 V
CLK Fall Time (2 V–0.8 V)
CLK Rise Time (0.8 V–2 V)
A31–A2, PWT, PCD, BE3–BE0, M/IO, D/C, CACHE,
W/R, ADS, LOCK, FERR, BREQ, HLDA,
SMIACT, HITM Valid Delay
A31–A2, PWT, PCD, BE3–BE0, M/IO, D/C, CACHE,
W/R, ADS, LOCK Float Delay
PCHK Valid Delay
BLAST, PLOCK, Valid Delay
BLAST, PLOCK, Float Delay
D31–D0, DP3–DP0 Write Data Valid Delay
D31–D0, DP3–DP0 Write Data Float Delay
EADS, INV, WB/WT Setup Time
EADS, INV, WB/WT Hold Time
KEN, BS16, BS8 Setup Time
KEN, BS16, BS8 Hold Time
RDY, BRDY Setup Time
RDY, BRDY Hold Time
HOLD, AHOLD Setup Time
BOFF Setup Time
HOLD, AHOLD, BOFF Hold Time
RESET, FLUSH, A20M, NMI, INTR, IGNNE,
STPCLK, SRESET, SMI Setup Time
RESET, FLUSH, A20M, NMI, INTR, IGNNE,
STPCLK, SRESET, SMI Hold Time
D31–D0, DP3–DP0, A31–A4 Read Setup Time
D32–D0, DP3–DP0, A31–A4 Read Hold Time
1.
Specifications assume C
L
= 50 pF. I/O Buffer model must be used to determine delays due to loading (trace and
component). First-order I/O buffer models for the processor are available.
2.
0-MHz operation guaranteed during stop clock operation or 1x Static Clock mode.
3.
Not 100% tested. Guaranteed by design characterization.
4.
For faster transitions (>0.1% between adjacent clocks), use the Stop Clock protocol to switch operating frequency.
5.
All timings are referenced at 1.5 V (as illustrated in the listed figures) unless otherwise noted.
11
11
ns
ns
ns
ns
39
39
39
39
3
3
t
6
3
14
ns
40
t
7
3
20
ns
41
Note 3
t
8
t
8a
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
18a
t
19
3
3
3
3
3
5
3
5
3
14
14
20
14
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
42
40
41
40
41
43
43
43
43
Note 3
Note 3
5
3
6
7
3
ns
ns
ns
ns
ns
44
44
43
43
43
t
20
5
ns
43
Note 5
t
21
3
ns
43
Note 5
t
22
t
23
5
3
ns
ns
43, 44
43, 44
Notes:
相關PDF資料 |
PDF描述 |
|---|---|
| AM486DX | Am486DX - Am486DX Block Diagram |
| AM486DXPGA | Am486DX PGA - Am486DX PGA Package Temperature Comparisons |
| AM486DXSQFP | 70NS, PLCC, IND TEMP(EEPROM) |
| AM486 | Am486 Microprocessor Software User＇s Manual? 4.40MB (PDF) |
| AM49DL3208G | Am49DL3208G - Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM486DE2-66V8TGC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:8-Kbyte Write-Through Embedded Microprocessor |
| AM486DE2-66V8THC | 制造商:Advanced Micro Devices 功能描述:Microprocessor, 32 Bit, 208 Pin, Plastic, QFP |
| AM486DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am486DX - Am486DX Block Diagram |
| AM486DX/DX2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am486DX/DX2 Hardware Reference Manual |
| AM486DX2 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am5X86⑩ Microprocessor Family |
發(fā)布緊急采購，3分鐘左右您將得到回復。