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參數(shù)資料
| 型號： | AM486DE2 |
| 英文描述： | Am486DE2 Microprocessor Data Sheet |
| 中文描述： | Am486DE2微處理器數(shù)據(jù)表 |
| 文件頁數(shù)： | 18/52頁 |
| 文件大?。?/td> | 1242K |
| 代理商： | AM486DE2 |
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18
Am486DE2 Microprocessor
specific memory region requirements. All bus masters,
such as DMA controllers, must reflect all data transfers
on the microprocessor local bus so that the micropro-
cessor can respond appropriately.
Cacheability
The Am486DE2 processor caches data based on the
state of the CD and NW bits in CR0, in conjunction with
the KEN signal, at the time of a burst read access from
memory. When the WB/WT signal is Low during the first
BRDY, KEN meets the standard setup and hold require-
ments, and the four 32-bit doublewords are placed in
the cache. However, all cacheable accesses in this
mode are considered write-through.
Note:
The CD bit in CR0 enables (0) or disables (1) the
internal cache. The NW bit in CR0 enables (0) or dis-
ables (1) write-through and snooping cycles. RESET
sets CD and NW to 1. Unlike RESET, however, SRESET
does not invalidate the cache nor does it modify the
values of CD and NW in CR0.
Write-Through
When the WB/WT signal is Low during the first BRDY
of the cache line read access, the cache line is consid-
ered a write-through access. Therefore, all writes to this
location in the cache are reflected on the external bus,
even if the cache line is write protected.
CLOCK CONTROL
Clock Generation
The Am486DE2 CPU is driven by a 1X clock that relies
on phased-lock loop (PLL) to generate the two internal
clock phases: phase one and phase two. The rising
edge of CLK corresponds to the start of phase one (ph1).
All external timing parameters are specified relative to
the rising edge of CLK.
Stop Clock
The Am486DE2 CPU also provides an interrupt mech-
anism, STPCLK, that allows system hardware to control
the power consumption of the CPU by stopping the in-
ternal clock to the CPU core in a sequenced manner.
The first low-power state is called the Stop Grant state.
If the CLK input is completely stopped, the CPU enters
into the Stop Clock state (the lowest power state). When
the CPU recognizes a STPCLK interrupt, the processor:
I
stops execution on the next instruction boundary
(unless superseded by a higher priority interrupt)
I
waits for completion of cache flush
I
stops the pre-fetch unit
I
empties all internal pipelines and write buffers
I
generates a Stop Grant bus cycle
I
stops the internal clock
At this point the CPU is in the Stop Grant state
The CPU cannot respond to a STPCLK request from an
HLDA state because it cannot empty the write buffers
and, therefore, cannot generate a Stop Grant cycle. The
rising edge of STPCLK signals the CPU to return to pro-
gram execution at the instruction following the interrupt-
ed instruction. Unlike the normal interrupts (INTR and
NMI), STPCLK does not initiate interrupt acknowledge
cycles or interrupt table reads.
External Interrupts in Order of Priority
In Write-through mode, the priority order of external in-
terrupts is:
1. RESET/SRESET
2. FLUSH
3. SMI
4. NMI
5. INTR
6. STPCLK
STPCLK is active Low and has an internal pull-up resis-
tor. STPCLK is asynchronous, but setup and hold times
must be met to ensure recognition in any specific clock.
STPCLK must remain active until the Stop Grant special
bus cycle is asserted and the system responds with ei-
ther RDY or BRDY. When the CPU enters the Stop
Grant state, the internal pull-up resistor is disabled, re-
ducing the CPU power consumption. The STPCLK input
must be driven High (not floated) to exit the Stop Grant
state. STPCLK must be deasserted for a minimum of
five clocks after RDY or BRDY is returned active for the
Stop Grant bus cycle before being asserted again.
There are two regions for the Low-Power-mode supply
current:
1. Low Power: Stop Grant state (fast wake-up,
frequency- and voltage-dependent)
2. Lowest Power: Stop Clock state (slow wake-up,
voltage-dependent)
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