參數(shù)資料
型號(hào): AM42DL16X2D
英文描述: 150NS, CERDIP, 883C; LEV B COMPLIANT(EEPROM)
中文描述: Am42DL16x2D -堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁(yè)數(shù): 9/60頁(yè)
文件大?。?/td> 956K
代理商: AM42DL16X2D
8
Am42DL16x2D
March 4, 2002
P R E L I M I N A R Y
PIN DESCRIPTION
A0–A16
= 17 Address Inputs (Common)
A–1, A19–A17 = 4 Address Inputs (Flash)
DQ15–DQ0
= 16 Data Inputs/Outputs (Common)
CE#f
= Chip Enable (Flash)
CE#s
= Chip Enable (SRAM)
OE#
= Output Enable (Common)
WE#
= Write Enable (Common)
RY/BY#
= Ready/Busy Output
UB#s
= Upper Byte Control (SRAM)
LB#s
= Lower Byte Control (SRAM)
CIOf
= I/O Configuration (Flash)
CIOf = V
IH
= Word mode (x16),
CIOf = V
IL
= Byte mode (x8)
= Hardware Reset Pin, Active Low
RESET#
WP#/ACC
= Hardware Write Protect/
Acceleration Pin (Flash)
V
CC
f
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
V
CC
s
V
SS
NC
= SRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
LOGIC SYMBOL
17
16
DQ15–DQ0
A16–A0
CE#f
OE#
WE#
RESET#
UB#s
RY/BY#
WP#/ACC
A–1, A19–A17
LB#s
CIOf
CE1#s
CE2s
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