參數(shù)資料
型號： AM42DL16X2D
英文描述： 150NS, CERDIP, 883C; LEV B COMPLIANT(EEPROM)
中文描述： Am42DL16x2D -堆疊式多芯片封裝（MCP）閃存和SRAM
文件頁數(shù)： 58/60頁
文件大?。?/td> 956K
代理商： AM42DL16X2D
March 4, 2002
Am42DL16x2D
57
P R E L I M I N A R Y
SRAM DATA RETENTION CHARACTERISTICS
Note:
CE1#s
≥
V
CC
– 0.2 V, CE2s
≥
V
CC
– 0.2 V (CE1#s controlled) or CE2s
≤
0.2 V (CE2s controlled), CIOs = V
SS
or V
CC
.
Figure 33.
CE1#s Controlled Data Retention Mode
Figure 34.
CE2s Controlled Data Retention Mode
Parameter
Symbol
Parameter Description
Test Setup
Min
Typ
Max
Unit
V
DR
V
CC
for Data Retention
CS1#s
≥
V
CC
– 0.2 V (See Note)
V
CC
= 1.5 V, CE1#s
≥
V
CC
– 0.2 V
(See Note)
1.5
3.3
V
I
DH
Data Retention Current
0.5
2
μA
t
SDR
t
RDR
Data Retention Set-Up Time
See data retention waveforms
0
ns
Recovery Time
t
RC
ns
V
DR
V
CC
2.7V
2.2V
CE1#s
GND
Data Retention Mode
CE1#s
≥
V
CC
-
0.2 V
t
SDR
t
RDR
V
CC
2.7 V
CE2s
0.4 V
GND
V
DR
Data Retention Mode
t
SDR
t
RDR
CE2s < 0.2 V
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