- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄364671 > AM42DL16X2D 150NS, CERDIP, 883C; LEV B COMPLIANT(EEPROM) PDF資料下載
參數(shù)資料
| 型號： | AM42DL16X2D |
| 英文描述： | 150NS, CERDIP, 883C; LEV B COMPLIANT(EEPROM) |
| 中文描述： | Am42DL16x2D -堆疊式多芯片封裝（MCP）閃存和SRAM |
| 文件頁數(shù)： | 15/60頁 |
| 文件大小： | 956K |
| 代理商： | AM42DL16X2D |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
14
Am42DL16x2D
March 4, 2002
P R E L I M I N A R Y
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE#f and RESET# pins are both held at V
CC
± 0.3 V.
(Note that this is a more restricted voltage range than
V
IH
.) If CE#f and RESET# are held at V
IH
, but not
within V
CC
± 0.3 V, the device will be in the standby
mode, but the standby current will be greater. The de-
vice requires standard access time (t
CE
) for read
access when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
CC3
in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
ACC
+
30 ns. The automatic sleep mode is independent of
the CE#f, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
CC4
in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the
RESET# pin is driven low for at least a period of t
RP
,
the device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
± 0.3 V, the de-
vice draws CMOS standby current (I
CC4
). If RESET# is
held at V
IL
but not within V
SS
± 0.3 V, the standby cur-
rent will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
READY
(during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is
completed within a time of t
READY
(not during Embed-
ded Algorithms). The system can read data t
RH
after
the RESET# pin returns to V
IH
.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 15 for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The output pins are placed in the high
impedance state.
Table 3.
Device Bank Division
Device
Part Number
Bank 1
Bank 2
Megabits
Sector Sizes
Megabits
Sector Sizes
Am29DL161D
0.5 Mbit
Eight 8 Kbyte/4 Kword
15.5 Mbit
Thirty-one
64 Kbyte/32 Kword
Am29DL162D
2 Mbit
Eight 8 Kbyte/4 Kword,
three 64 Kbyte/32 Kword
14 Mbit
Twenty-eight
64 Kbyte/32 Kword
Am29DL163D
4 Mbit
Eight 8 Kbyte/4 Kword,
seven 64 Kbyte/32 Kword
12 Mbit
Twenty-four
64 Kbyte/32 Kword
Am29DL164D
8 Mbit
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
8 Mbit
Sixteen
64 Kbyte/32 Kword
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM42DL16X4D | 150NS, PLCC, IND TEMP(EEPROM) |
| AM42DL32X4G | 150NS, 32LCC, 883C; LEV B COMPLIANT(EEPROM) |
| AM42DL6402G | 150NS, SOIC, IND TEMP(EEPROM) |
| AM42DL6404G | 64 Mbit (8 M x 8-Bit/4 M x 16-Bit) CMOS and 4 Mbit (256 K x 16-Bit) Static RAM (Preliminary) |
| AM42DL640AG | 200NS, CERDIP, 883C; LEV B COMPLIANT(EEPROM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM42DL16X4D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am42DL16x4D - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM42DL3224GB25IT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (256 K x 16-Bit) Static RAM |
| AM42DL3224GB30IT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (256 K x 16-Bit) Static RAM |
| AM42DL3224GB35IT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (256 K x 16-Bit) Static RAM |
| AM42DL3224GB40IT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (256 K x 16-Bit) Static RAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。