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| 型號(hào)： | AM41PDS3224DB11FS |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA73 |
| 封裝： | 8 X 11.60 MM, FBGA-73 |
| 文件頁(yè)數(shù)： | 49/59頁(yè) |
| 文件大小： | 1072K |
| 代理商： | AM41PDS3224DB11FS |
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52
Am41PDS3224D
May 13, 2002
P R E L IMINARY
SRAM AC CHARACTERISTICS
Write Cycle
Notes:
1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing.
2. t
CW is measured from CE1#s going low to the end of write.
3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (t
WP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write.
Figure 30.
SRAM Write Cycle—WE# Control
Parameter
Symbol
Description
10, 11
Unit
tWC
Write Cycle Time
Min
70
ns
t
Cw
Chip Enable to End of Write
Min
60
ns
tAS
Address Setup Time
Min
0
ns
t
AW
Address Valid to End of Write
Min
60
ns
tBW
UB#s, LB#s to End of Write
Min
60
ns
t
WP
Write Pulse Time
Min
50
ns
tWR
Write Recovery Time
Min
0
ns
tWHZ
Write to Output High-Z
Min
0
ns
Max
20
t
DW
Data to Write Time Overlap
Min
30
ns
tDH
Data Hold from Write Time
Min
0
ns
t
OW
End Write to Output Low-Z
min
5
ns
Address
CS1#s
Data Undefined
UB#s, LB#s
WE#
Data In
Data Out
tWC
tCW
(See Note 2)
tAW
High-Z
Data Valid
CS2s
tCW
(See Note 2)
tBW
tWP
(See Note 5)
tAS
(See Note 4)
tWR (See Note 3)
tWHZ
tDW
tDH
tOW
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