參數(shù)資料
型號： AM41PDS3224DB11FS
廠商： SPANSION LLC
元件分類： 存儲器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA73
封裝： 8 X 11.60 MM, FBGA-73
文件頁數(shù)： 4/59頁
文件大?。?/td> 1072K
代理商： AM41PDS3224DB11FS
May 13, 2002
Am41PDS3224D
11
P R E L IMINARY
Table 2.
Device Bus Operations—SRAM Byte Mode, CIOs = V
SS
Legend: L = Logic Low = V
IL, H = Logic High = VIH, VID = 9–11 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address Input, Byte Mode,
SADD = Flash Sector Address, A
IN = Address In, DIN = Data In, DOUT = Data Out, DNU = Do Not Use
Notes:
1.
Other operations except for those indicated in this column are inhibited.
2.
Do not apply CE#f = V
IL, CE1#s = VIL and CE2s = VIH at the same time.
3.
Don’t care or open LB#s or UB#s.
4.
If WP#/ACC = V
IL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = V
ACC (9V), the program time will be reduced by 40%.
5.
The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection
6.
If WP#/ACC = V
IL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on
whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC =
V
HH, all sectors will be unprotected.
Operation
(Notes 1, 2)
CE#f
CE1#s
CE2s
OE# WE#
SA
Addr.
LB#s
UB#s
RESET#
WP#/ACC
DQ7–
DQ0
DQ15–
DQ8
Read from Flash
L
HX
LH
X
A
IN
XX
H
L/H
D
OUT
D
OUT
XL
Write to Flash
L
HX
HL
X
A
IN
XX
H
D
IN
D
IN
XL
Standby
V
CC ±
0.3 V
HX
XX
X
V
CC ±
0.3 V
H
High-Z
XL
Output Disable
L
H
SA
X
DNU
H
L/H
High-Z
Flash Hardware
Reset
X
HX
X
L
L/H
High-Z
XL
Sector Protect (Note
L
HX
HL
X
SADD,
A6 = L,
A1 = H,
A0 = L
XX
V
ID
L/H
D
IN
X
XL
Sector Unprotect
L
HX
HL
X
SADD,
A6 = H,
A1 = H,
A0 = L
XX
V
ID
D
IN
X
XL
Temporary Sector
Unprotect
X
HX
XX
X
A
IN
XX
V
ID
D
IN
High-Z
XL
Read from SRAM
H
L
H
L
H
SA
A
IN
XX
H
X
D
OUT
High-Z
Write to SRAM
H
L
H
X
L
SA
A
IN
XX
H
X
D
IN
High-Z
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