參數(shù)資料
型號(hào): AM41PDS3224DB11FS
廠商: SPANSION LLC
元件分類: 存儲(chǔ)器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA73
封裝: 8 X 11.60 MM, FBGA-73
文件頁數(shù): 33/59頁
文件大?。?/td> 1072K
代理商: AM41PDS3224DB11FS
38
Am41PDS3224D
May 13, 2002
P R E L IMINARY
FLASH AC CHARACTERISTICS
Read-Only Operations
Notes:
1. Not 100% tested.
2. See Figure 12 and Table 12 for test specifications.
3. Measurements performed by placing a 50
termination on the data pin with a bias of V
CC/2. The time from OE# high to the
data bus driven to V
CC/2 is taken as tDFAC Characteristics.
Parameter
Description
Test Setup
Speed Option
JEDEC
Std
10
11
Unit
tAVAV
tRC
Read Cycle Time (Note 1)
Min
100
110
ns
t
AVQV
t
ACC
Address to Output Delay
CE#, OE# = V
IL
Max
100
110
ns
tPRC
Page Read Cycle
Min
40
45
ns
t
PACC
Page Address to Output Delay
CE#, OE# = V
IL
Max
40
45
ns
tELQV
tCE
Chip Enable to Output Delay
OE# = VIL
Max
100
110
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
35
45
ns
tEHQZ
tDF
Chip Enable to Output High Z (Notes 1, 3)
Max
16
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Notes 1, 3)
Max
16
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
Min
0
ns
t
OEH
Output Enable Hold
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
tOH
tCE
Outputs
WE#
Addresses
CE#f
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tRH
tOE
tRH
0 V
RY/BY#
RESET#
tDF
Figure 15.
Conventional Read Operation Timings
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