參數(shù)資料
型號: AM41LV3204M
英文描述: Stacked Multi-chip Package (MCP) 32 Mbit (4 M x 8 bit/2 M x 16-bit) Flash Memory and 4 Mbit (512K x 8-Bit/256 K x 16-Bit) Static RAM (Preliminary)
中文描述: 堆疊式多芯片封裝(MCP)32兆位(4個M × 8位/ 2米x 16位)閃存和4兆位(為512k × 8-Bit/256畝x 16位),靜態(tài)存儲器(初步)
文件頁數(shù): 2/67頁
文件大?。?/td> 1030K
代理商: AM41LV3204M
PRELIMINARY
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.
Publication#
30119
Issue Date:
June 10, 2003
Rev:
A
Amendment/
+1
Am41LV3204M
Stacked Multi-chip Package (MCP) 32 Mbit (4 M x 8 bit/2 M x 16-bit) Flash
Memory and 4 Mbit (512K x 8-Bit/256 K x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
Power supply voltage of 2.7 to 3.3 volt
High Performance
— Access time as fast as 100ns initial 30 ns page Flash
70 ns SRAM
Package
— 69-Ball FBGA
— 8 x 10 x 1.2 mm
Operating Temperature
— –40
°
C to +85
°
C
Flash Memory Features
ARCHITECTURAL ADVANTAGES
Single power supply operation
— 3 V for read, erase, and program operations
Manufactured on 0.23 μm MirrorBit process
technology
SecSi
(Secured Silicon) Sector region
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
— May be programmed and locked at the factory or by
the customer
Flexible sector architecture
— Sixty-three 32 Kword/64-kbyte sectors
— Eight 4 Kword/8-kbyte boot sectors
Compatibility with JEDEC standards
— Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
Minimum 100,000 erase cycle guarantee per sector
°
C
PERFORMANCE CHARACTERISTICS
High performance
— 100 ns access time
— 30 ns page read times
— 0.5 s typical sector erase time
— 15 μs typical write buffer word programming time:
16-word/32-byte write buffer reduces overall
programming time for multiple-word updates
— 4-word/8-byte page read buffer
— 16-word/32-byte write buffer
Low power consumption (typical values at 3.0 V, 5
MHz)
— 30 mA typical initial Page read current; 10 mA typical
intra-Page read current
— 50 mA typical erase/program current
— 1 μA typical standby mode current
SOFTWARE & HARDWARE FEATURES
Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
Hardware features
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
— Temporary Sector Unprotect: V
ID
-level method of
changing code in locked sectors
— WP#/ACC input:
Write Protect input (WP#) protects top or bottom two
sectors regardless of sector protection settings
ACC (high voltage) accelerates programming time for
higher throughput during system production
— Hardware reset input (RESET#) resets device
SRAM Features
Power dissipation
— Operating: 30 mA maximum
— Standby: 10 μA maximum
CE1s# and CE2s Chip Select
Power down features using CE1s# and CE2s
Data retention supply voltage: 1.5 to 3.3 volt
Byte data control: LB#s (DQ7–DQ0),
UB#s (DQ15–DQ8)
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