參數(shù)資料
型號(hào)： AM30LV0064DJ40F2I
英文描述： 8-SOIC (WIDE BODY) IND TEMP, GREEN(BIOS FLASH)
中文描述： NAND型閃存EEPROM
文件頁(yè)數(shù)： 14/41頁(yè)
文件大?。?/td> 859K
代理商： AM30LV0064DJ40F2I
14
Am30LV0064D
Read Operations
Read Data (00h / 01h)
There are two commands available for reading from
the Flash array (via the Data Registers). These are
Read Data—(starting with the) First Half Page (00h)
and Read Data—(starting with the) Second Half Page
(01h).
The commands are identical except for the starting re-
gion within the selected page. After the command
cycle, three address cycles are used to input the start-
ing address for the read operation. Upon the rising
edge of the final WE# pulse there is a 7 μs latency in
which 528 bytes of information are transferred from
the Flash array page to the 528 byte Data Register.
During the 7 μs latency period the Flash device will ap-
pear busy and either the RY/BY# signal or the status
register may be used to monitor the completion of the
data transfer. Only the Reset and Read Status com-
mands are valid during the period that the device is
busy. Once the information has been loaded into the
Data Register, it may be sequentially read with con-
secutive 50 ns RE# pulses. Each RE# pulse will
automatically advance the column address by one.
Once the last column has been read, the page address
will automatically increment by one and the Data Regis-
ter will be updated with information from the new page
after a 7 μs latency period.
During the sequential read mode, if the Spare Area
Enable input (SE#) is high, the column address will ad-
vance to address 511 and then the page address will
increment by one. If the SE# input is low, the column
address will advance to address 527 before the page
address is incremented. This allows information in the
Spare Area to be read at the end of the page before
the next page of information is transferred into the
Data Registers. In the case of the Read Data com-
mand, the SE# input may go low anytime from before
the command is issued to before address 510 is ac-
cessed. This allows the Flash internal logic to correctly
enable the Spare Area for reading.
Notes:
1.
CE# is don’t care in between WE# and RE# transitions.
2. Falling edge of CE# to valid data must be >45 ns.
3. CE# transition when RY/BY# is low terminates read operation.
4. ALE must remain high for entire address latch operation; no transitions allowed.
Figure 2.
Read Data
CE#
CLE
ALE
WE#
RE#
I/O7-0
SE#
RY/BY#
CMD
Start Address
Read Page
Read Next Page
Read Next Page
Data Transfer
Data Transfer
Data Transfer
Read Data (00h or 01h)
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM30LV0064DJ40F2IT 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology
AM30LV0064DJ40WGI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NAND Flash EEPROM
AM30LV0064DJ40WGIT 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology
AM30N02-40D 制造商:ANALOGPOWER 制造商全稱:ANALOGPOWER 功能描述:N-Channel 20-V (D-S) MOSFET
AM30N02-59D 制造商:ANALOGPOWER 制造商全稱:ANALOGPOWER 功能描述:N-Channel 20-V (D-S) MOSFET
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