參數(shù)資料
型號(hào)： AM30LV0064DJ40F2I
英文描述： 8-SOIC (WIDE BODY) IND TEMP, GREEN(BIOS FLASH)
中文描述： NAND型閃存EEPROM
文件頁數(shù)： 12/41頁
文件大?。?/td> 859K
代理商： AM30LV0064DJ40F2I
12
Am30LV0064D
Table 4.
Am30LV0064D Command Definitions
Legend:
WR = Write Cycle Byte, RD = Read Cycle, SA = Starting Address, Etc. = previous sequence continues as needed,
SR = Status Register, AR = Address Register, DR = Data Register, BA = Block Address Byte
Notes:
1. All values are in hexadecimal.
2. See Table 2 for description of bus operations.
3. The Gapless Read command is similar to the Read Data
Area commands except that the 7 μs latency does not
occur when the Page address pointer steps to the next
page to be read. This command requires that the starting
byte address is located within the first half of the selected
Page.
4. For the Read Spare Area command it is necessary for the
SE# pin to be low during the CLE cycle and when actively
reading from the 16 byte Spare Area. For all other
commands the SE# pin must be low at least two cycles
prior to the first spare area access at byte address 512 (low
before byte address 510).
5. The two byte Block Address cycles load address bits
A22–A9 into the device. Since only address bits A22–A13
are required for a Block address, address bits A12–A9 are
don’t care.
6. The system may read and program in non-erasing Blocks
when in the Erase Suspend mode. The Erase Suspend
command is valid only during a Block erase operation.
7. The Erase Resume command is valid only during the Erase
Suspend mode
8. The fifth bus cycle for read operations follows the read
latency delay.
Command Sequence
(Note 2)
Read Data Area–First Half Page
Read Data Area–Second Half
Page
Read Data Area–Gapless Read
(Note 3)
Read Spare Area (Note 4)
Read ID
Read Status
Input Data
Program Data
Block Erase (Note 5)
Erase Suspend (Note 6)
Erase Resume (Note 8)
Reset
Bus Cycles (Note 1)
Third
Oper.
Data
WR
SA
First
Second
Oper.
WR
Fourth
Oper.
WR
Fifth (Note 8)
Oper.
RD
Sixth
Oper.
WR
Data
00
Data
SA
Data
SA
Data
Data
Oper.
Etc.
Data
Etc.
WR
01
WR
SA
WR
SA
WR
SA
RD
Data
Etc.
Etc.
WR
02
WR
SA
WR
SA
WR
SA
RD
Data
Etc.
Etc.
WR
WR
WR
WR
WR
WR
WR
WR
WR
50
90
70
80
10
60
B0
D0
FF
WR
WR
RD
WR
SA
00
SR
SA
WR
RD
Etc.
WR
SA
01
Etc.
SA
WR
RD
SA
E6
RD
Data
Etc.
Etc.
WR
SA
WR
Data
Etc.
Etc.
WR
BA
WR
BA
WR
D0
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