- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362196 > AK7706VT Consumer IC PDF資料下載
參數(shù)資料
| 型號： | AK7706VT |
| 英文描述： | Consumer IC |
| 中文描述： | 消費性IC |
| 文件頁數(shù)： | 41/52頁 |
| 文件大?。?/td> | 1085K |
| 代理商： | AK7706VT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁當(dāng)前第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
[ASAHI KASEI] [AK7706]
<M0058-E-01>
1999/10
- 41 -
7-1-e) External conditional jump code write (during reset phase)
The data comprising a set of two bytes is used to perform an external conditional jump code write operation. The data can be inputed
during both the reset and operation phases, and the input data are set to the specified register at the leading edge of the LRCLK. When
all data bits have been transferred, the RDY terminal goes to "L". Upon completion of writing, it goes to "H". A jump command will
be executed if there is any one agreement between "1" of each bit of external condition code 8 bits (soft set) plus 1 bit (hard set) at the
external input terminal JX and "1" of each bit of the IFCON field. The data during the reset phase can be written only before release of
the reset, after all data has been transferred. RQ Transition from "L" to "H" in the write operation during the reset phase must be
execured after three LRCLK in the slave mode, one LRCLK in master mode, respectively, from the trailing edge of the LRCLK after
release of the reset. Then the RDY goes to "H" after capturing the rise of the next LRCLK. A write operation from the microcomputer
is disabled until the RDY goes to "H". The IFCON field provides external conditions written on the program.
Note: It should be noted that the LRCLK phase is inverted in the I2S-compatible state.
7
0 JX
External condition code
nnnnnnnno
á
Check if there is any one agreement between the bit specified
in IFCON and "1" in the external condition code
16
a
8
IFCON field
uuuuuuuu
Data transfer procedure
Command code C4h ( 1 1 0 0 0 1 0 0)
Code data (D7 . . . . . D0)
Timing for external conditional jump write operation (during reset phase)
RDY
RESET
11000100 D7 . . . D0
SI
SO
SCLK
RQ
2LRCLK(max)
LRCLK
L ch R ch
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK7716VT | Consumer IC |
| AK80A-024L-033F40 | Analog IC |
| AK80A-024L-050F30 | Analog IC |
| AK80A-024L-120F14 | Analog IC |
| AK80A-024L-150F12 | Analog IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK7712 | 制造商:AKM 制造商全稱:AKM 功能描述:Built-in 20-bit ADC/DAC Sophisticated Audio DSP |
| AK7712A-VT | 制造商:AKM 制造商全稱:AKM 功能描述:Built-in 20-bit ADC/DAC Sophisticated Audio DSP |
| AK7712AVTP | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:BUILT-IN 20-BIT ADC/DAC SOPHISTICATED AUDIO DSP |
| AK7714 | 制造商:AKM 制造商全稱:AKM 功能描述:20-Bit Audio Codec with DSP and Delay RAM |
| AK7714VT | 制造商:AKM 制造商全稱:AKM 功能描述:20-Bit Audio Codec with DSP and Delay RAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。