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參數(shù)資料
| 型號(hào)： | AK7706VT |
| 英文描述： | Consumer IC |
| 中文描述： | 消費(fèi)性IC |
| 文件頁數(shù)： | 32/52頁 |
| 文件大?。?/td> | 1085K |
| 代理商： | AK7706VT |
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[ASAHI KASEI] [AK7706]
<M0058-E-01>
1999/10
- 32 -
(4) Resetting
The AK7706 has two reset pins: INIT RESET and DSP RESET .
The INIT RESET pin is used to initialize the AK7706, as shown in "Power supply startup sequence section 3)."
The system is reset when DSP RESET = "L" and CODEC RESET = "L". (Description of "reset" is for "system reset".)
Under the condition of system reset, the program write operation is normally performed (except for write operation during running).
CLKO is output even during the system reset phase if CTRL = “L”, but LRCLK and BITCLK in the master mode will be inactive.
The system reset is released by setting DSP RESET to "H", and this will activate the internal counter. This counter generates
LRCLK and BITCLK in the master mode: however, a hazard may occur when a clock signal is generated. When the system reset is
released in the slave mode, internal timing will be actuated in synchronization with "
á
" of LRCLK (when the standard input format is
used). Timing between the external and internal clocks is adjusted at this time. If the phase difference in LRCLK and internal timing is
within about -1/16 to 1/16 of the input sampling cycle (1/fs) during the operation, the operation is performed with internal timing
remaining unchanged. If the phase difference exceeds the above range, the phase is adjusted by synchronization with "
á
" of LRCLK
(when the standard input format is used). This is a circuit to prevent failure of synchronization with the external circuit. For some time
after returning to the normal state after loss of synchronization, normal data will not be valid. If you want to change the clock, do so
while the system is in reset.
When DSP RESET is set to “H”, the reset state is cancelled, and the external RAM clear (“0” data writes ) and the internal DRAM
clear are executed from the rising edge of LRCLK. This period takes 12400 * 1/fs [sec] at 512fs mode and 16540 * 1/fs [sec] at 384fs
mode. ( fs : sampling frequency ). After this “data reset function”, the function of [ 7-3) Write during RUN phase ] is acceptable.
The AK7706 performs normal operation when both DSP RESET is set to "H".
After the internal control circuit issues a reset pulse, the AK7716 will write all 0 data into all-internal RAM and external RAM.
It takes 12,500LRCLK(max) whatever external RAM selected. (LRCLK = 1/fs, fs=44.1kHz : 283ms , fs=48kHz : 260ms ) See.2-2)-
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PDF描述 |
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| AK7716VT | Consumer IC |
| AK80A-024L-033F40 | Analog IC |
| AK80A-024L-050F30 | Analog IC |
| AK80A-024L-120F14 | Analog IC |
| AK80A-024L-150F12 | Analog IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK7712 | 制造商:AKM 制造商全稱:AKM 功能描述:Built-in 20-bit ADC/DAC Sophisticated Audio DSP |
| AK7712A-VT | 制造商:AKM 制造商全稱:AKM 功能描述:Built-in 20-bit ADC/DAC Sophisticated Audio DSP |
| AK7712AVTP | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:BUILT-IN 20-BIT ADC/DAC SOPHISTICATED AUDIO DSP |
| AK7714 | 制造商:AKM 制造商全稱:AKM 功能描述:20-Bit Audio Codec with DSP and Delay RAM |
| AK7714VT | 制造商:AKM 制造商全稱:AKM 功能描述:20-Bit Audio Codec with DSP and Delay RAM |
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