Revision 16 3-3 FF Flash*Freeze Mode Activation Pin The FF pin is a dedicated input pin used to enter and exit Fl" />
參數(shù)資料
型號： AGLP125V2-CS281I
廠商： Microsemi SoC
文件頁數(shù)： 132/134頁
文件大?。?/td> 0K
描述： IC FPGA IGLOO PLUS 125K 281-CSP
標(biāo)準(zhǔn)包裝： 184
系列： IGLOO PLUS
邏輯元件/單元數(shù)： 3120
RAM 位總計： 36864
輸入/輸出數(shù)： 212
門數(shù)： 125000
電源電壓： 1.14 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 281-TFBGA，CSBGA
供應(yīng)商設(shè)備封裝： 281-CSP（10x10）
IGLOO PLUS Low Power Flash FPGAs
Revision 16
3-3
FF
Flash*Freeze Mode Activation Pin
The FF pin is a dedicated input pin used to enter and exit Flash*Freeze mode. The FF pin is active low,
has the same characteristics as a single-ended I/O, and must meet the maximum rise and fall times.
When Flash*Freeze mode is not used in the design, the FF pin is available as a regular I/O.
When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering
Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted.
The Flash*Freeze pin can be used with any single-ended I/O standard supported by the I/O bank in
which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin
should be treated as a sensitive asynchronous signal. When defining pin placement and board layout,
simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be
considered.
Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both
Flash*Freeze mode and normal operation mode. No user intervention is required.
Table 3-1 shows the Flash*Freeze pin location on the available packages for IGLOO and ProASIC3L
devices. The Flash*Freeze pin location is independent of device (except for a PQ208 package), allowing
migration to larger or smaller IGLOO devices while maintaining the same pin location on the board. Refer
to the "Flash*Freeze Technology and Low Power Modes" chapter of the IGLOO PLUS Device Family
User’s Guide for more information on I/O states during Flash*Freeze mode.
Table 3-1 Flash*Freeze Pin Location in IGLOO PLUS Devices
Package
Flash*Freeze Pin
CS281
W2
CS201
R4
CS289
U1
VQ128
34
VQ176
47
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AGLP125-V2CS289 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP125V2-CS289 功能描述:IC FPGA IGLOO PLUS 125K 289-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO PLUS 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
AGLP125-V2CS289ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP125-V2CS289I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP125V2-CS289I 功能描述:IC FPGA IGLOO PLUS 125K 289-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO PLUS 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
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