2-76 Revision 16 Timing Characteristics 1.5 V DC Core Voltage Table 2-96 FIFO
參數(shù)資料
型號(hào): AGLP125V2-CS281I
廠商: Microsemi SoC
文件頁數(shù): 125/134頁
文件大?。?/td> 0K
描述: IC FPGA IGLOO PLUS 125K 281-CSP
標(biāo)準(zhǔn)包裝: 184
系列: IGLOO PLUS
邏輯元件/單元數(shù): 3120
RAM 位總計(jì): 36864
輸入/輸出數(shù): 212
門數(shù): 125000
電源電壓: 1.14 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 281-TFBGA,CSBGA
供應(yīng)商設(shè)備封裝: 281-CSP(10x10)
IGLOO PLUS DC and Switching Characteristics
2-76
Revision 16
Timing Characteristics
1.5 V DC Core Voltage
Table 2-96 FIFO
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
Std.
Units
tENS
REN, WEN Setup Time
1.66
ns
tENH
REN, WEN Hold Time
0.13
ns
tBKS
BLK Setup Time
0.30
ns
tBKH
BLK Hold Time
0.00
ns
tDS
Input Data (WD) Setup Time
0.63
ns
tDH
Input Data (WD) Hold Time
0.20
ns
tCKQ1
Clock High to New Data Valid on RD (flow-through)
2.77
ns
tCKQ2
Clock High to New Data Valid on RD (pipelined)
1.50
ns
tRCKEF
RCLK High to Empty Flag Valid
2.94
ns
tWCKFF
WCLK High to Full Flag Valid
2.79
ns
tCKAF
Clock High to Almost Empty/Full Flag Valid
10.71
ns
tRSTFG
RESET Low to Empty/Full Flag Valid
2.90
ns
tRSTAF
RESET Low to Almost Empty/Full Flag Valid
10.60
ns
tRSTBQ
RESET Low to Data Out Low on RD (flow-through)
1.68
ns
RESET Low to Data Out Low on RD (pipelined)
1.68
ns
tREMRSTB
RESET Removal
0.51
ns
tRECRSTB
RESET Recovery
2.68
ns
tMPWRSTB
RESET Minimum Pulse Width
0.68
ns
tCYC
Clock Cycle Time
6.24
ns
FMAX
Maximum Frequency for FIFO
160
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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