- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄15529 > ADZS-BF537-STAMP (Analog Devices Inc)SYSTEM DEV FOR ADSP-BF537 PDF資料下載
參數(shù)資料
| 型號： | ADZS-BF537-STAMP |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | SYSTEM DEV FOR ADSP-BF537 |
| 產(chǎn)品培訓(xùn)模塊： | Blackfin® STAMP BSP Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | DSP |
| 適用于相關(guān)產(chǎn)品： | ADSP-BF537 |
| 所含物品： | ADSP-BF537 STAMP 板和軟件 |
| 配用： | ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARD |
| 相關(guān)產(chǎn)品： | ADSP-BF537KBCZ-6BV-ND - IC DSP CTLR 16BIT 208CSPBGA ADSP-BF537BBCZ-5BV-ND - IC DSP CTLR 16BIT 208CSPBGA ADSP-BF537KBCZ-6AV-ND - IC DSP CTLR 16BIT 182CSPBGA ADSP-BF537BBCZ-5AV-ND - IC DSP CTLR 16BIT 182CSPBGA ADSP-BF537BBCZ-5B-ND - IC DSP CTLR 16BIT 208CSPBGA ADSP-BF537BBC-5A-ND - IC DSP CTLR 16BIT 182CSPBGA |
| 其它名稱： | ADDS-BF537-STAMP ADDS-BF537-STAMP-ND |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
Rev. J
|
Page 12 of 68
|
February 2014
Programmable Rx address filters, including a 64-bit
address hash table for multicast and/or unicast frames, and
programmable filter modes for broadcast, multicast, uni-
cast, control, and damaged frames.
Advanced power management supporting unattended
transfer of Rx and Tx frames and status to/from external
memory via DMA during low power sleep mode.
System wake-up from sleep operating mode upon magic
packet or any of four user-definable wake-up frame filters.
Support for 802.3Q tagged VLAN frames.
Programmable MDC clock rate and preamble suppression.
In RMII operation, 7 unused pins can be configured as
GPIO pins for other purposes.
PORTS
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors
group the many peripheral signals to four ports—Port F, Port G,
Port H, and Port J. Most of the associated pins are shared by
multiple signals. The ports function as multiplexer controls.
Eight of the pins (Port F7–0) offer high source/high sink current
capabilities.
General-Purpose I/O (GPIO)
The processors have 48 bidirectional, general-purpose I/O
(GPIO) pins allocated across three separate GPIO modules—
PORTFIO, PORTGIO, and PORTHIO, associated with Port F,
Port G, and Port H, respectively. Port J does not provide GPIO
functionality. Each GPIO-capable pin shares functionality with
other processor peripherals via a multiplexing scheme; however,
the GPIO functionality is the default state of the device upon
power-up. Neither GPIO output or input drivers are active by
default. Each general-purpose port pin can be individually con-
trolled by manipulation of the port control, status, and interrupt
registers:
GPIO direction control register – Specifies the direction of
each individual GPIO pin as input or output.
GPIO control and status registers – The processors employ
a “write one to modify” mechanism that allows any combi-
nation of individual GPIO pins to be modified in a single
instruction, without affecting the level of any other GPIO
pins. Four control registers are provided. One register is
written in order to set pin values, one register is written in
order to clear pin values, one register is written in order to
toggle pin values, and one register is written in order to
specify a pin value. Reading the GPIO status register allows
software to interrogate the sense of the pins.
GPIO interrupt mask registers – The two GPIO interrupt
mask registers allow each individual GPIO pin to function
as an interrupt to the processor. Similar to the two GPIO
control registers that are used to set and clear individual
pin values, one GPIO interrupt mask register sets bits to
enable interrupt function, and the other GPIO interrupt
mask register clears bits to disable interrupt function.
GPIO pins defined as inputs can be configured to generate
hardware interrupts, while output pins can be triggered by
software interrupts.
GPIO interrupt sensitivity registers – The two GPIO inter-
rupt sensitivity registers specify whether individual pins are
level- or edge-sensitive and specify—if edge-sensitive—
whether just the rising edge or both the rising and falling
edges of the signal are significant. One register selects the
type of sensitivity, and one register selects which edges are
significant for edge-sensitivity.
PARALLEL PERIPHERAL INTERFACE (PPI)
The processor provides a parallel peripheral interface (PPI) that
can connect directly to parallel ADC and DAC converters, video
encoders and decoders, and other general-purpose peripherals.
The PPI consists of a dedicated input clock pin, up to three
frame synchronization pins, and up to 16 data pins. The input
clock supports parallel data rates up to half the system clock rate
and the synchronization signals can be configured as either
inputs or outputs.
The PPI supports a variety of general-purpose and ITU-R 656
modes of operation. In general-purpose mode, the PPI provides
half-duplex, bidirectional data transfer with up to 16 bits of
data. Up to three frame synchronization signals are also pro-
vided. In ITU-R 656 mode, the PPI provides half-duplex
bidirectional transfer of 8- or 10-bit video data. Additionally,
on-chip decode of embedded start-of-line (SOL) and start-of-
field (SOF) preamble packets is supported.
General-Purpose Mode Descriptions
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications.
Three distinct submodes are supported:
1. Input mode – Frame syncs and data are inputs into the PPI.
2. Frame capture mode – Frame syncs are outputs from the
PPI, but data are inputs.
3. Output mode – Frame syncs and data are outputs from the
PPI.
Input Mode
Input mode is intended for ADC applications, as well as video
communication with hardware signaling. In its simplest form,
PPI_FS1 is an external frame sync input that controls when to
read data. The PPI_DELAY MMR allows for a delay (in PPI_
CLK cycles) between reception of this frame sync and the initia-
tion of data reads. The number of input data samples is user
programmable and defined by the contents of the PPI_COUNT
register. The PPI supports 8-bit and 10-bit through 16-bit data,
programmable in the PPI_CONTROL register.
Frame Capture Mode
Frame capture mode allows the video source(s) to act as a slave
(for frame capture for example). The ADSP-BF534/
ADSP-BF536/ADSP-BF537 processors control when to read
from the video source(s). PPI_FS1 is an HSYNC output and
PPI_FS2 is a VSYNC output.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BQ2057PDGKR | IC LI-ION LDO CHRG MGMT 8-MSOP |
| RBM12DCST | CONN EDGECARD 24POS DIP .156 SLD |
| BQ2057PDGKG4 | IC LI-ION LDO CHRG MGMT 8-MSOP |
| EVAL-ADAU1701MINIZ | BOARD EVAL SIGMADSP AUD ADAU1701 |
| RBA15DTMI | CONN EDGECARD 30POS R/A .125 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADZS-BF537-STAMP | 制造商:Analog Devices 功能描述:Microcontroller Development Tool |
| ADZS-BF538-EZLITE | 制造商:Analog Devices 功能描述:- Bulk |
| ADZSBF538FEZLITE | 制造商:Analog Devices 功能描述:RES Wirewound 6927 75Ohm 1% 3W 20PPM SMD T/R |
| ADZS-BF538F-EZLITE | 功能描述:BOARD EVAL FOR ADSP-BF538 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:Blackfin® 產(chǎn)品培訓(xùn)模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產(chǎn)品:Blackfin? BF50x Series Processors 標(biāo)準(zhǔn)包裝:1 系列:Blackfin® 類型:DSP 適用于相關(guān)產(chǎn)品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤，光學(xué)撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關(guān)產(chǎn)品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| ADZS-BF538F-EZLITE | 制造商:Analog Devices 功能描述:Microcontroller Development Tool |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。