參數(shù)資料
型號(hào): ADZS-BF537-STAMP
廠商: Analog Devices Inc
文件頁(yè)數(shù): 36/68頁(yè)
文件大?。?/td> 0K
描述: SYSTEM DEV FOR ADSP-BF537
產(chǎn)品培訓(xùn)模塊: Blackfin® STAMP BSP
Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
標(biāo)準(zhǔn)包裝: 1
系列: Blackfin®
類型: DSP
適用于相關(guān)產(chǎn)品: ADSP-BF537
所含物品: ADSP-BF537 STAMP 板和軟件
配用: ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARD
相關(guān)產(chǎn)品: ADSP-BF537KBCZ-6BV-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537BBCZ-5BV-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537KBCZ-6AV-ND - IC DSP CTLR 16BIT 182CSPBGA
ADSP-BF537BBCZ-5AV-ND - IC DSP CTLR 16BIT 182CSPBGA
ADSP-BF537BBCZ-5B-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537BBC-5A-ND - IC DSP CTLR 16BIT 182CSPBGA
其它名稱: ADDS-BF537-STAMP
ADDS-BF537-STAMP-ND
Rev. J
|
Page 41 of 68
|
February 2014
Table 33. External Late Frame Sync
Parameter
Min
Max
Unit
Switching Characteristics
tDDTLFSE
Data Delay from Late External TFSx or External RFSx with MCMEN = 1, MFD = 0
1, 2
10.0
ns
tDTENLFS
Data Enable from Late FS or MCMEN = 1, MFD = 01, 2
0ns
1 MCMEN = 1, TFSx enable and TFSx valid follow tDDTENFS and tDDTLFS.
2 If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2, then tDDTE/I and tDTENE/I apply, otherwise tDDTLFSE and tDTENLFS apply.
Figure 23. External Late Frame Sync
RSCLKx
RFSx
DTx
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
EXTERNAL RFSx IN MULTI-CHANNEL MODE
1ST BIT
tDTENLFSE
tDDTLFSE
TSCLKx
TFSx
DTx
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
LATE EXTERNAL TFSx
1ST BIT
tDDTLFSE
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