參數(shù)資料
型號: ADZS-BF537-STAMP
廠商: Analog Devices Inc
文件頁數(shù): 29/68頁
文件大?。?/td> 0K
描述: SYSTEM DEV FOR ADSP-BF537
產(chǎn)品培訓(xùn)模塊: Blackfin® STAMP BSP
Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
標準包裝: 1
系列: Blackfin®
類型: DSP
適用于相關(guān)產(chǎn)品: ADSP-BF537
所含物品: ADSP-BF537 STAMP 板和軟件
配用: ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARD
相關(guān)產(chǎn)品: ADSP-BF537KBCZ-6BV-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537BBCZ-5BV-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537KBCZ-6AV-ND - IC DSP CTLR 16BIT 182CSPBGA
ADSP-BF537BBCZ-5AV-ND - IC DSP CTLR 16BIT 182CSPBGA
ADSP-BF537BBCZ-5B-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537BBC-5A-ND - IC DSP CTLR 16BIT 182CSPBGA
其它名稱: ADDS-BF537-STAMP
ADDS-BF537-STAMP-ND
Rev. J
|
Page 35 of 68
|
February 2014
External DMA Request Timing
Table 28 and Figure 15 describe the external DMA request
operations.
Table 28. External DMA Request Timing
Parameter
Min
Max
Unit
Timing Requirements
tDS
DMARx Asserted to CLKOUT High Setup
6.0
ns
tDH
CLKOUT High to DMARx Deasserted Hold Time
0.0
ns
tDMARACT
DMARx Active Pulse Width
1.0 × tSCLK
ns
tDMARINACT
DMARx Inactive Pulse Width
1.75 × tSCLK
ns
Figure 15. External DMA Request Timing
CLKOUT
tDS
DMAR0/1
(ACTIVE LOW)
DMAR0/1
(ACTIVE HIGH)
tDMARACT
tDMARINACT
tDH
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