
REV. 0
ADV7197
–16–
COLOR Y
CY (CY7–CY0)
(Address (SR4–SR0) = 06H)
CY7
CY6
CY5
CY4
CY3
CY2
CY1
CY0
CY7–CY0
COLOR Y VALUE
Figure 21. Color Y Register
COLOR CR
CCR (CCR7–CCR0)
(Address (SR4–SR0) = 07H)
CCR7
CCR6
CCR5
CCR4
CCR3
CCR2
CCR1
CCR0
CCR7
–
CCR0
COLOR CR VALUE
Figure 22. Color Cr Register
COLOR CB
CCB (CCB7–CCB0)
(Address (SR4–SR0) = 08H)
CCB7
CCB6
CCB5
CCB4
CCB3
CCB2
CCB1
CCB0
CCB7
–
CCB0
COLOR CB VALUE
Figure 23. Color Cb Register
These three 8-bit-wide registers are used to program the output
color of the internal test pattern generator, be it the lines of the
cross hatch pattern or the uniform field test pattern.
The standard used for the values for Y and the color difference
signals to obtain white, black and the saturated primary and comple-
mentary colors conforms to the ITU-R BT 601-4 standard.
The Table III shows sample color values to be programmed into
the color registers.
Table III. Sample Color Values
Sample
Color
Color Y
Value
Color Cr
Value
Color Cb
Value
White
Black
Red
Green
Blue
Yellow
Cyan
Magenta
235 (EB)
16 (10)
81 (51)
145 (91)
41 (29)
210 (D2)
170 (AA)
106 (6A)
128 (80)
128 (80)
240 (F0)
34 (22)
110 (6E)
146 (92)
16 (10)
222 (DE)
128 (80)
128 (80)
90 (5A)
54 (36)
240 (F0)
16 (10)
166 (A6)
202 (CA)
DAC TERMINATION AND LAYOUT CONSIDERATIONS
Voltage Reference
The ADV7197 contains an on-board voltage reference. The
V
REF
pin is normally terminated to V
AA
through a 0.1
μ
F capacitor
when the internal V
REF
is used. Alternatively, the ADV7197
can be used with an external V
REF
(AD589).
Resistor R
SET
is connected between the R
SET
pin and analog
ground and is used to control the full scale output current and
therefore the DAC voltage output levels. For full-scale output
R
SET
must have a value of 2470
. R
LOAD
has a value of 300
.
When an input range of 0–1023 is selected the value of R
SET
must be 2820
.
The ADV7197 has three analog outputs, corresponding to Y,
Pr, Pb video signals. The DACs must be used with external
buffer circuits in order to provide sufficient current to drive an
output device. A suitable op amp would be the AD8057.
PC BOARD LAYOUT CONSIDERATIONS
The ADV7197 is optimally designed for lowest noise perfor-
mance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV7197, it is imperative
that great care be given to the PC board layout.
The layout should be optimized for lowest noise on the ADV7197
power and ground lines. This can be achieved by shielding the
digital inputs and providing good decoupling. The lead length
between groups of V
AA
and AGND and V
DD
and DGND pins
should be kept as short as possible to minimized inductive ringing.
It is recommended that a four-layer printed circuit board is
used. With power and ground planes separating the layer of the
signal carrying traces of the components and solder side layer.
Placement of components should consider to separate noisy
circuits, such as crystal clocks, high-speed logic circuitry and
analog circuitry.
There should be a separate analog ground plane (AGND) and
a separate digital ground plane (GND).
Power planes should encompass a digital power plane (V
DD
) and a
analog power plane (V
AA
). The analog power plane should contain
the DACs and all associated circuitry, and the V
REF
circuitry.
The digital power plane should contain all logic circuitry. The
analog and digital power planes should be individually connected
to the common power plane at one single point through a suit-
able filtering device, such as a ferrite bead.
DAC output traces on a PCB should be treated as transmission
lines. It is recommended that the DACs be placed as close as
possible to the output connector, with the analog output traces
being as short as possible (less than 3 inches. The DAC termi-
nation resistors should be placed as close as possible to the DAC
outputs and should overlay the PCB’s ground plane. As well as
minimizing reflections, short analog output traces will reduce
noise pickup due to neighboring digital circuitry.