參數(shù)資料
型號(hào)： ADV7197KST
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： Multiformat HDTV Encoder with Three 11-Bit DACs
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP52
封裝： PLASTIC, MQFP-52
文件頁(yè)數(shù)： 12/20頁(yè)
文件大?。?/td> 229K
代理商： ADV7197KST
REV. 0
ADV7197
–12–
MODE REGISTER 0
MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)
Figure 14 shows the various operations under the control of
Mode Register 0.
MR0 BIT DESCRIPTION
Output Standard Selection (MR00–MR01)
These bits are used to select the output levels from the ADV7197.
If EIA 770.3 (MR01–00 = “00”) is selected, the output levels will
be: 0 mV for blanking level, 700 mV for peak white (Y channel),
±
350 mV for Pr, Pb outputs and –300 mV for tri-level sync.
If Full Input Range (MR01–00 = “10”) is selected, the output
levels will be 700 mV for peak white for the Y channel,
±
350 mV
for Pr, Pb outputs, and –300 mV for Sync. This mode is used
for RS-170, RS-343A standard output compatibility.
Sync insertion on the Pr, Pb channels is optional. For output
levels refer to the Appendix.
Input Control Signals (MR02–MR03)
These control bits are used to select whether data is input with
external horizontal, vertical, and blanking sync signals or if the
data is input with embedded EAV/SAV codes. An Asynchro-
nous timing mode is also available using TSYNC,
SYNC
and
DV as input control signals.
These timing control signals have to be programmed by the user
and are used for any other high definition standard input but
SMPTE274M and SMPTE296M.
Figure 12 shows an example of how to program the ADV7197
to accept a different high definition standard but SMPTE274M
or SMPTE296M.
Reserved (MR04)
A “0” must be written to this bit.
Input Standard (MR05)
Select between 1080i or 720p input.
DV Polarity (MR06)
This control bit allows to select the polarity of the DV input
control signal to be either active high or active low. This is in
order to facilitate interfacing from input devices which use an
active high blanking signal output.
Reserved (MR07)
A “0” must be written to this bit.
CLK
SYNC
TSYNC
DV
SET
MR06 =
‘
1
’
PROGRAMMABLE
INPUT TIMING
ANALOG
OUTPUT
ACTIVE VIDEO
HORIZONTAL SYNC
81
66
66
243
1920
A
B
C
D
E
Figure 12. Async Timing Mode—Programming Input Control Signals for SMPTE295M Compatibility
747
748
749
750
1
2
3
4
5
6
7
8
25
26
27
744
745
DISPLAY
VERTICAL BLANKING INTERVAL
DISPLAY
DV
VSYNC
HSYNC
Figure 13. DV Input Control Signal in Relation to Video Output Signal for SMPTE296M (720p)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7197KSZ 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT HDTV ENCODER, 3 11-BIT DACS - Bulk
ADV7202 制造商:AD 制造商全稱:Analog Devices 功能描述:Simultaneous Sampling Video Rate Codec
ADV7202KST 制造商:Rochester Electronics LLC 功能描述:27MHZ DTV PICTURE IN PICTURE CODEC I.C. - Bulk 制造商:Analog Devices 功能描述:
ADV7202KSTZ 功能描述:IC CODEC VIDEO 10BIT 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
ADV7280ABCPZ-M 功能描述:10-BIT SD VIDEO DECODER 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:視頻 數(shù)據(jù)接口:I2C，串行 分辨率（位）:10 b ADC/DAC 數(shù):1 / 0 三角積分:無 信噪比，ADC/DAC（db）（典型值）:- 動(dòng)態(tài)范圍，ADC/DAC（db）（典型值）:- 電壓 - 電源，模擬:1.71 V ~ 1.89 V 電壓 - 電源，數(shù)字:1.71 V ~ 1.89 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-WQ（5x5） 標(biāo)準(zhǔn)包裝:1
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