參數(shù)資料
型號: ADV7180BSTZ
廠商: ANALOG DEVICES INC
元件分類: 顏色信號轉換
英文描述: 10-Bit, 4 x Oversampling SDTV Video Decoder
中文描述: COLOR SIGNAL DECODER, PQFP64
封裝: 10 X 10 MM, ROHS COMPLIANT, MS-026BCD, LQFP-64
文件頁數(shù): 87/112頁
文件大小: 1320K
代理商: ADV7180BSTZ
ADV7180
Rev. A | Page 87 of 112
Bits (Shading Indicates Default
State)
6
5
4
Comments
Subaddress
0x2D
Register
Chroma Gain
Control 1
Bit Description
CMG[11:8]/CG[11:8]. In
manual mode, the
chroma gain control can
be used to program a
desired manual chroma
gain. In auto mode, it can
be used to read back the
current gain value.
Reserved.
CAGT[1:0]. Chroma
automatic gain timing
allows adjustment of
the chroma AGC
tracking speed.
CMG[7:0]/CG[7:0].
Chroma manual gain
lower eight bits. See
CMG[11:8]/CG[11:8] for
description.
LMG[11:8]/LG[11:8]. In
manual mode, luma gain
control can be used to
program a desired
manual chroma gain. In
auto mode, it can be
used to read back the
actual gain value used.
Reserved.
LAGT[1:0]. Luma
automatic gain timing
allows adjustment of
the luma AGC tracking
speed.
LMG[7:0]/LG[7:0]. Luma
manual gain lower eight
bits. See LMG[11:8]/
LG[11:8] for description.
7
3
0
2
1
1
0
0
0
LQFP-64
LFCSP-40
Notes
CAGC[1:0] settings decide
in which mode CMG[11:0]
operates
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
Set to 1
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Fast (TC = 0.2 sec)
Adaptive
CMG[11:0] = 750d; gain is 1
in NTSC. CMG[11:0] = 741d;
gain is 1 in PAL
Has an effect only if
CAGC[1:0] is set to
autogain (10)
0x2E
Chroma Gain
Control 2
Min value is 0 dec
(G = 1/1000)
Max value is 3750 dec
(Gain = 5)
x
x
x
x
LAGC[1:0] settings decide
in which mode LMG[11:0]
operates
0
0
1
1
x
0
1
0
1
x
1
x
1
x
x
x
x
x
Set to 1
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Fast (TC = 0.2 sec)
Adaptive
LMG[11:0] = 1600d;
gain is 1 in NTSC
LMG[11:0] = 1630d;
gain is 1 in PAL
Only has an effect if
LAGC[1:0] is set to auto
gain (001, 010, 011,or 100)
0x2F
Luma Gain Control 1
0x30
Luma Gain Control 2
Minimum value
NTSC 2048 (G = 0.5)
PAL 2048 (G = 0.5)
Maximum value
NTSC 4095 (G = 2)
PAL 4095 (G = 2)
HSE = Hsync end
HSB = Hsync begin
0x31
Reserved.
HVSTIM. Selects where
within a line of video
the VS signal is asserted.
NEWAVMODE. Sets the
EAV/SAV mode.
0
1
0
1
0
Set to default
Start of line relative to HSE
Start of line relative to HSB
0
EAV/SAV codes generated
to suit Analog Devices
encoders
Manual VS/FIELD position
controlled by the 0x32, 0x33,
and 0xE5 to 0xEA registers
Set to default
Set to default
VS goes high in the middle
of the line (even field)
VS changes state at the
start of the line (even field)
VS goes high in the middle
of the line (odd field)
VS changes state at the
start of the line (odd field)
Set to default
VS goes low in the middle
of the line (even field)
VS changes state at the
start of the line (even field)
VS goes low in the middle
of the line (odd field)
VS changes state at the
start of the line odd field
1
0x32
VS/FIELD Control 1
Reserved.
Reserved.
VSBHE.
0
0
0
0
0
0
0
0
0
1
NEWAVMODE bit must be
set high
1
VSBHO.
0
VS/FIELD Control 2
1
Reserved.
VSEHE.
0
0
0
0
1
0
0
NEWAVMODE bit must be
set high
1
0
0x33
VS/FIELD Control 3
VSEHO.
1
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參數(shù)描述
ADV7180BSTZ 制造商:Analog Devices 功能描述:Video IC
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