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ADV7180
Address
Dec Hex Register Name
154 9A CCAP 2
155 9B
Letterbox 1
156 9C Letterbox 2
157 9D Letterbox 3
178 B2
CRC
195 C3 ADC Switch 1
196 C4 ADC Switch 2
220 DC Letterbox Control 1
221 DD Letterbox Control 2
222 DE ST Noise Readback 1
223 DF ST Noise Readback 2
224 E0
Reserved
225 E1
SD Offset Cb
226 E2
SD Offset Cr
227 E3
SD Saturation Cb
228 E4
SD Saturation Cr
229 E5
NTSC V Bit Begin
230 E6
NTSC V Bit End
231 E7
NTSC F Bit Toggle
232 E8
PAL V Bit Begin
233 E9
PAL V Bit End
234 EA PAL F Bit Toggle
235 EB
Vblank Control 1
236 EC Vblank Control 2
243 F3
AFE_CONTROL 1
Rev. A | Page 77 of 112
RW 7
R
R
R
R
W
RW MUX1[3]
RW MAN_MUX_EN
RW
RW LB_SL[3]
R
R
ST_NOISE[7]
RW SD_OFF_CB[7] SD_OFF_CB[6] SD_OFF_CB[5] SD_OFF_CB[4] SD_OFF_CB[3] SD_OFF_CB[2]
RW SD_OFF_CR[7] SD_OFF_CR[6] SD_OFF_CR[5] SD_OFF_CR[4] SD_OFF_CR[3] SD_OFF_CR[2]
RW SD_SAT_CB[7] SD_SAT_CB[6] SD_SAT_CB[5] SD_SAT_CB[4] SD_SAT_CB[3] SD_SAT_CB[2]
RW SD_SAT_CR[7] SD_SAT_CR[6] SD_SAT_CR[5] SD_SAT_CR[4] SD_SAT_CR[3] SD_SAT_CR[2]
RW NVBEGDELO
NVBEGDELE
NVBEGSIGN
RW NVENDDELO
NVENDDELE
NVENDSIGN
RW NFTOGDELO
NFTOGDELE
NFTOGSIGN
RW PVBEGDELO
PVBEGDELE
PVBEGSIGN
RW PVENDDELO
PVENDDELE
PVENDSIGN
RW PFTOGDELO
PFTOGDELE
PFTOGSIGN
RW NVBIOLCM[1]
NVBIOLCM[0]
NVBIELCM[1] NVBIELCM[0]
RW NVBIOCCM[1]
NVBIOCCM[0]
NVBIECCM[1] NVBIECCM[0]
RW
6
CCAP2[6]
LB_LCT[6]
LB_LCM[6]
LB_LCB[6]
MUX1[2]
5
CCAP2[5]
LB_LCT[5]
LB_LCM[5]
LB_LCB[5]
MUX1[1]
LB_SL[1]
ST_NOISE[5]
4
CCAP2[4]
LB_LCT[4]
LB_LCM[4]
LB_LCB[4]
MUX1[0]
LB_TH[4]
LB_SL[0]
ST_NOISE[4]
3
CCAP2[3]
LB_LCT[3]
LB_LCM[3]
LB_LCB[3]
MUX0[3]
MUX2[3]
LB_TH[3]
LB_EL[3]
ST_NOISE_VLD ST_NOISE[10]
ST_NOISE[3]
2
CCAP2[2]
LB_LCT[2]
LB_LCM[2]
LB_LCB[2]
CRC_ENABLE
MUX0[2]
MUX2[2]
LB_TH[2]
LB_EL[2]
1
CCAP2[1]
LB_LCT[1]
LB_LCM[1]
LB_LCB[1]
MUX0[1]
MUX2[1]
LB_TH[1]
LB_EL[1]
ST_NOISE[9]
ST_NOISE[1]
SD_OFF_CB[1] SD_OFF_CB[0]
SD_OFF_CR[1] SD_OFF_CR[0]
SD_SAT_CB[1] SD_SAT_CB[0]
SD_SAT_CR[1] SD_SAT_CR[0]
NVBEG[1]
NVEND[1]
NFTOG[1]
PVBEG[1]
PVEND[1]
PFTOG[1]
PVBIELCM.1
PVBIECCM.1
AA_FILT_EN[1] AA_FILT_EN[0]
0
CCAP2[0]
LB_LCT[0]
LB_LCM[0]
LB_LCB[0]
MUX0[0]
MUX2[0]
LB_TH[0]
LB_EL[0]
ST_NOISE[8]
ST_NOISE[0]
Reset
Value
–
–
–
–
00011100 1C
xxxxxxxx 00
0xxxxxxx 00
10101100 AC
01001100 4C
–
–
10000000 80
10000000 80
10000000 80
10000000 80
00100101 25
00000100 04
01100011 63
01100101 65
00010100 14
01100011 63
01010101 55
01010101 55
00000000 00
(Hex)
–
–
–
–
CCAP2[7]
LB_LCT[7]
LB_LCM[7]
LB_LCB[7]
LB_SL.2
ST_NOISE.6
–
–
ST_NOISE[2]
NVBEG[4]
NVEND[4]
NFTOG[4]
PVBEG[4]
PVEND[4]
PFTOG[4]
NVBEG[3]
NVEND[3]
NFTOG[3]
PVBEG[3]
PVEND[3]
PFTOG[3]
PVBIOLCM.1
PVBIOCCM.1
AA_FILT_
MAN_OVR
DR_STR_C[1]
VS_COAST_
MODE[1]
PEAKING_
GAIN[3]
DNR_TH2[3]
NVBEG[2]
NVEND[2]
NFTOG[2]
PVBEG[2]
PVEND[2]
PFTOG[2]
PVBIOLCM.0
PVBIOCCM.0
AA_FILT_EN[2]
NVBEG[0]
NVEND[0]
NFTOG[0]
PVBEG[0]
PVEND[0]
PFTOG[0]
PVBIELCM.0
PVBIECCM.0
244 F4
248 F8
249 F9
Drive Strength
IF Comp Control
VS Mode Control
RW
RW
RW
DR_STR[1]
DR_STR[0]
DR_STR_C[0]
IFFILTSEL[2]
VS_COAST_
MODE[0]
PEAKING_
GAIN[2]
DNR_TH2[2]
DR_STR_S[1]
IFFILTSEL[1]
EXTEND_VS_
MIN_FREQ
PEAKING_
GAIN[1]
DNR_TH2[1]
DR_STR_S[0]
IFFILTSEL[0]
EXTEND_VS_
MAX_FREQ
PEAKING_
GAIN[0]
DNR_TH2[0]
xx010101 15
00000000 00
00000011 03
251 FB
Peaking Control
RW PEAKING_
GAIN[7]
RW DNR_TH2[7]
PEAKING_
GAIN[6]
DNR_TH2[6]
PEAKING_
GAIN[5]
DNR_TH2[5]
PEAKING_
GAIN[4]
DNR_TH2[4]
01000000 40
252 FC Coring Threshold
1
This feature applies to the ADV7180BCPZ 40-lead only because VS or field are shared on a single pin (Pin 37).
2
This feature applies to the ADV7180BSTZ 64-lead only.
00000100 04
Table 102. Interrupt System Register Map Details
1
Address
Dec
Hex
Register Name
R/W
64
40
Interrupt
Config. 1
66
42
Interrupt
Status 1
67
43
Interrupt Clear 1
W
7
INTRQ_DUR_
SEL[1]
6
INTRQ_DUR_
SEL[0]
MV_PS_CS_Q
5
MV_INTRQ_
SEL[1]
SD_FR_
CHNG_Q
SD_FR_
CHNG_CLR
SD_FR_
CHNG_MSKB
4
MV_INTRQ_
SEL[0]
3
2
MPU_STIM_
INTRQ
1
INTRQ_OP_
SEL[1]
SD_UNLOCK
_Q
SD_UNLOCK_
CLR
SD_UNLOCK_
MSKB
0
INTRQ_OP_SE
L[0]
SD_LOCK_Q
Reset
Value
0001x000
(Hex)
10
RW
R
–
–
MV_PS_CS_
CLR
MV_PS_CS_
MSKB
SD_LOCK_
CLR
SD_LOCK_
MSKB
CCAPD
x0000000
00
68
44
Interrupt
Mask 1
Raw
Status 1
Interrupt
Status 2
Interrupt Clear 2
RW
x0000000
00
69
45
R
MPU_STIM_I
NTRQ
MPU_STIM_
INTRQ_Q
MPU_STIM_
INTRQ_CLR
MPU_STIM_
INTRQ_MSKB
EVEN_FIELD
–
–
70
46
R
SD_FIELD_
CHNGD_Q
SD_FIELD_
CHNGD_CLR
SD_FIELD_
CHNGD_MSK
B
SCM_LOCK
GEMD_Q
CCAPD_Q
–
–
71
47
W
GEMD_CLR
CCAPD_CLR
0xx00000
00
72
48
Interrupt
Mask 2
RW
GEMD_MSKB
CCAPD_
MSKB
0xx00000
00
73
49
Raw
Status 2
Interrupt
Status 3
Interrupt Clear 3
R
SD_H_LOCK
SD_V_LOCK
SD_OP_50Hz
–
–
74
4A
R
PAL_SW_LK_
CHNG_Q
PAL_SW_LK_
CHNG_CLR
PAL_SW_LK_
CHNG_MSKB
SCM_LOCK_
CHNG_Q
SCM_LOCK_
CHNG_CLR
SCM_LOCK_
CHNG_MSKB
VDP_GS_
VPS_PDC_
UTC_CHNG_
Q
VDP_GS_
VPS_PDC_
UTC_CHNG_
CLR
SD_AD_
CHNG_Q
SD_AD_
CHNG_CLR
SD_AD_
CHNG_MSKB
SD_H_LOCK_
CHNG_Q
SD_H_LOCK_
CHNG_CLR
SD_H_LOCK_
CHNG_MSKB
VDP_CGMS_
WSS_
CHNGD_Q
SD_V_LOCK_
CHNG_Q
SD_V_LOCK_
CHNG_CLR
SD_V_LOCK_
CHNG_MSKB
SD_OP_
CHNG_Q
SD_OP_
CHNG_CLR
SD_OP_
CHNG_MSKB
VDP_CCAPD_
Q
–
–
75
4B
W
xx000000
00
76
4C
Interrupt
Mask 3
Interrupt
Status 4
RW
xx000000
00
78
4E
R
VDP_VITC_Q
–
–
79
4F
Interrupt Clear 4
W
VDP_VITC_
CLR
VDP_CGMS_
WSS_CHNGD
_CLR
VDP_CCAPD_
CLR
00x0x0x0
00