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參數(shù)資料
| 型號(hào)： | ADV7180BSTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 91/116頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO DECODER SDTV 64-LQFP |
| 產(chǎn)品變化通告： | ADV7180 Metal Mask Edit 22/Oct/2009 |
| 設(shè)計(jì)資源： | Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060) Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻解碼器 |
| 應(yīng)用： | 數(shù)碼相機(jī)，手機(jī)，便攜式視頻 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADV7180BSTZ-REELDKR |
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ADV7180
Data Sheet
Rev. I | Page 76 of 116
PIXEL PORT CONFIGURATION
The ADV7180 has a very flexible pixel port that can be configured
in a variety of formats to accommodate downstream ICs.
Table 100, Table 101, and Table 102 summarize the various
functions that the ADV7180 pins can have in different modes of
operation.
The ordering of components, for example, Cr vs. Cb for
Channel A, Channel B, and Channel C can be changed. See the
indicates the default positions for the Cr/Cb components.
OF_SEL[3:0], Output Format Selection, Address 0x03[5:2]
The modes in which the ADV7180 pixel port can be configured
are under the control of OF_SEL[3:0]. See Table 102 for details.
The default LLC frequency output on the LLC pin is approximately
27 MHz. For modes that operate with a nominal data rate of
13.5 MHz (0001, 0010), the clock frequency on the LLC pin stays
at the higher rate of 27 MHz. For information on outputting the
nominal 13.5 MHz clock on the LLC pin, see the
Address 0x8F[6:4] section.
SWPC, Swap Pixel Cr/Cb, Address 0x27[7]
This bit allows Cr and Cb samples to be swapped.
When SWPC is 0 (default), no swapping is allowed.
When SWPC is 1, the Cr and Cb values can be swapped.
LLC_PAD_SEL[2:0] LLC Output Selection,
Address 0x8F[6:4]
The following I2C write allows the user to select between LLC
(nominally at 27 MHz) and LLC (nominally at 13.5 MHz).
The LLC signal is useful for LLC-compatible wide bus (16-bit)
output modes. See the OF_SEL[3:0], Output Format Selection,
Address 0x03[5:2] section for additional information. The LLC
signal and data on the data bus are synchronized. By default, the
rising edge of LLC/LLC is aligned with the Y data; the falling
edge occurs when the data bus holds C data. The polarity of the
clock, and therefore the Y/C assignments to the clock edges, can
be altered by using the polarity LLC pin.
When LLC_PAD_SEL is 000, the output is nominally 27 MHz
LLC on the LLC pin (default).
When LLC_PAD_SEL is 101, the output is nominally 13.5 MHz
LLC on the LLC pin.
Table 100. 64-Lead LQFP P15 to P0 Output/Input Pin Mapping
Data Port Pins P[15:0]
Format and Mode
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Video Out, 8-Bit, 4:2:2
YCrCb[7:0]OUT
Video Out, 16-Bit, 4:2:2
Y[7:0]OUT
CrCb[7:0]OUT
Table 101. 48-Lead, 40-Lead, and 32-Lead Devices P7 to P0 Output/Input Pin Mapping
Data Port Pins P[7:0]
Format and Mode
7
6
5
4
3
2
1
0
Video Out, 8-Bit, 4:2:2
YCrCb[7:0]OUT
Table 102. ADV7180 Standard Definition Pixel Port Modes
64-Lead LQFP P[15:0]
48-Lead LQFP, 40-Lead LFCSP, or 32-Lead LFCSP
OF_SEL[3:0]
Format
P[15:8]
P[7:0]
0000 to 0001
Reserved
Reserved, do not use
0010
16-bit at LLC 4:2:2
Y[7:0]
CrCb[7:0]
Not valid
0011 (default)
8-bit at LLC 4:2:2 (default)
YCrCb[7:0]
Three-state
YCrCb[7:0]
0100 to 1111
Reserved
Reserved, do not use
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