- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10627 > ADV7180BSTZ-REEL (Analog Devices Inc)IC VIDEO DECODER SDTV 64-LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | ADV7180BSTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 59/116頁 |
| 文件大小： | 0K |
| 描述： | IC VIDEO DECODER SDTV 64-LQFP |
| 產(chǎn)品變化通告： | ADV7180 Metal Mask Edit 22/Oct/2009 |
| 設(shè)計(jì)資源： | Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060) Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻解碼器 |
| 應(yīng)用： | 數(shù)碼相機(jī)，手機(jī)，便攜式視頻 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADV7180BSTZ-REELDKR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁當(dāng)前第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁
Data Sheet
ADV7180
Rev. I | Page 47 of 116
SYNCHRONIZATION OUTPUT SIGNALS
HS Configuration
The following controls allow the user to configure the behavior
of the HS output pin only:
Beginning of HS signal via HSB[10:0]
End of HS signal via HSE[10:0]
Polarity of HS using PHS
The HS begin (HSB) and HS end (HSE) registers allow the user
to freely position the HS output (pin) within the video line. The
values in HSB[10:0] and HSE[10:0] are measured in pixel units
from the falling edge of HS. Using both values, the user can
program both the position and length of the HS output signal.
HSB[10:0], HS Begin, Address 0x34[6:4], Address 0x35[7:0]
The position of this edge is controlled by placing a binary
number into HSB[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV Code FF, 00, 00, XY (see Figure 37). HSB is set to
00000000010b, which is two LLC clock cycles from count [0].
The default value of HSB[10:0] is 0x02, indicating that the HS
pulse starts two pixels after the falling edge of HS.
HSE[10:0], HS End, Address 0x34[2:0], Address 0x36[7:0]
The position of this edge is controlled by placing a binary
number into HSE[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV Code FF, 00, 00, XY (see Figure 37). HSE is set to
00000000000b, which is 0 LLC clock cycles from count [0].
The default value of HSE[10:0] is 00, indicating that the HS
pulse ends 0 pixels after the falling edge of HS.
For example,
To shift the HS toward active video by 20 LLCs, add
20 LLCs to both HSB and HSE, that is,
HSB[10:0] = [00000010110], HSE[10:0] = [00000010100].
To shift the HS away from active video by 20 LLCs, add
1696 LLCs to both HSB and HSE (for NTSC), that is,
HSB[10:0] = [11010100010], HSE[10:0] = [11010100000].
Therefore, 1696 is derived from the NTSC total number of
pixels, 1716.
To move 20 LLCs away from active video, subtract 20 from
1716 and add the result in binary to both HSB[10:0] and
HSE[10:0].
PHS, Polarity HS, Address 0x37[7]
The polarity of the HS pin can be inverted using the PHS bit.
When PHS is 0 (default), HS is active low.
When PHS is 1, HS is active high.
Table 64. HS Timing Parameters (See Figure 37)
Standard
Characteristic
HS Begin Adjust
HSB[10:0] (Default)
HS End Adjust
HSE[10:0] (Default)
HS to Active Video
LLC Clock Cycles, C
in Figure 37 (Default)
Active Video Samples/
Line, D in Figure 37
Total LLC Clock
Cycles, E in Figure 37
NTSC
00000000010b
00000000000b
272
720Y + 720C = 1440
1716
PAL
00000000010b
00000000000b
284
720Y + 720C = 1440
1728
E
ACTIVE
VIDEO
LLC
PIXEL
BUS
HS
Cr
Y
FF
00
XY
80
10
80
10
80
10
FF
00
XY
Cb
Y
Cr
Y
Cb
Y
Cr
4 LLC
D
HSB[10:0]
HSE[10:0]
C
E
D
SAV
ACTIVE VIDEO
H BLANK
EAV
05700-
028
Figure 37. HS Timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX3485ECSA+ | IC TXRX RS485/422 10MBPS 8SOIC |
| VI-BWP-MX-F3 | CONVERTER MOD DC/DC 13.8V 75W |
| VI-BWP-MX-F2 | CONVERTER MOD DC/DC 13.8V 75W |
| VI-BWP-MW | CONVERTER MOD DC/DC 13.8V 100W |
| VE-2W2-IW-F2 | CONVERTER MOD DC/DC 15V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7180KCP32Z | 功能描述:IC VIDEO DECODER 10BIT 32LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| ADV7180KCP32Z-RL | 功能描述:IC VIDEO DECODER 10BIT 32LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| ADV7180KST48Z | 功能描述:IC VID DECOD SDTV 10BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| ADV7180KST48Z-RL | 功能描述:視頻 IC 48-Lead Low Profile Quad Flat Package RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| ADV7180WBCP32Z | 制造商:Analog Devices 功能描述:IC, 10-BIT 4X OVERSAMPLING SDTV DECODER 制造商:Analog Devices 功能描述:SDTV VIDEO DECODER 32-PIN LFCSP EP TRAY - Trays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。