The sequence for the interrupt-based reading of the VDP I2
參數(shù)資料
型號： ADV7180BSTZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 76/116頁
文件大?。?/td> 0K
描述： IC VIDEO DECODER SDTV 64-LQFP
產(chǎn)品變化通告： ADV7180 Metal Mask Edit 22/Oct/2009
設計資源： Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060)
Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
標準包裝： 1
類型： 視頻解碼器
應用： 數(shù)碼相機，手機，便攜式視頻
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應商設備封裝： 64-LQFP（10x10）
包裝： 標準包裝
其它名稱： ADV7180BSTZ-REELDKR
ADV7180
Data Sheet
Rev. I | Page 62 of 116
The sequence for the interrupt-based reading of the VDP I2C
data registers is as follows for the CCAP standard:
1. The user unmasks the CCAP interrupt mask bit (Register 0x50,
Bit 0, user sub map = 1). CCAP data occurs on the incoming
video. VDP slices CCAP data and places it into the VDP
readback registers.
2. The VDP CCAP available bit CC_CAP goes high, and the
VDP module signals to the interrupt controller to stimulate
an interrupt request (for CCAP in this case).
3. The user reads the interrupt status bits (user sub map) and
sees that new CCAP data is available (Register 0x4E, Bit 0,
user sub map = 1).
4. The user writes 1 to the CCAP interrupt clear bit (Register 0x4F,
Bit 0, user sub map = 1) in the interrupt I2C space (this is a
self-clearing bit). This clears the interrupt on the INTRQ
pin but does not have an effect in the VDP I2C area.
5. The user reads the CCAP data from the VDP I2C area.
6. The user writes to Bit CC_CLEAR in the
VDP_STATUS_CLEAR register, (Register 0x78, Bit 0,
user sub map = 1) to signify the CCAP data has been read
(therefore the VDP CCAP can be updated at the next
occurrence of CCAP).
7. The user goes back to Step 2.
Interrupt Mask Register Details
The following bits set the interrupt mask on the signal from the
VDP VBI data slicer.
VDP_CCAPD_MSK, Address 0x50[0], User Sub Map
Setting VDP_CCAPD_MSK to 0 (default) disables the interrupt
on the VDP_CCAPD_Q signal.
Setting VDP_CCAPD_MSK to 1 enables the interrupt on the
VDP_CCAPD_Q signal.
VDP_CGMS_WSS_CHNGD_MSK, Address 0x50[2], User
Sub Map
Setting VDP_CGMS_WSS_CHNGD_MSK to 0 (default) disables
the interrupt on the VDP_CGMS_WSS_ CHNGD_Q signal.
Setting VDP_CGMS_WSS_CHNGD_MSK to 1 enables the
interrupt on the VDP_CGMS_WSS_CHNGD_Q signal.
VDP_GS_VPS_PDC_UTC_CHNG_MSK,
Address 0x50[4], User Sub Map
Setting VDP_GS_VPS_PDC_UTC_CHNG_MSK to 0 (default)
disables the interrupt on the
VDP_GS_VPS_PDC_UTC_CHNG_Q signal.
Setting VDP_GS_VPS_PDC_UTC_CHNG_MSK to 1 enables
the interrupt on the VDP_GS_VPS_PDC_UTC_CHNG_Q signal.
VDP_VITC_MSK, Address 0x50[6], User Sub Map
Setting VDP_VITC_MSK to 0 (default) disables the interrupt
on the VDP_VITC_Q signal.
Setting VDP_VITC_MSK to 1 enables the interrupt on the
VDP_VITC_Q signal.
Interrupt Status Register Details
The following read-only bits contain data detection information
from the VDP module since the status bit is last cleared or
unmasked.
VDP_CCAPD_Q, Address 0x4E[0], User Sub Map
When VDP_CCAPD_Q is 0 (default), CCAP data is not
detected.
When VDP_CCAPD_Q is 1, CCAP data is detected.
VDP_CGMS_WSS_CHNGD_Q, Address 0x4E[2],
User Sub Map
When VDP_CGMS_WSS_CHNGD_Q is 0 (default), CGMS or
WSS data is not detected.
When VDP_CGMS_WSS_CHNGD_Q is 1, CGM or WSS data
is detected.
VDP_GS_VPS_PDC_UTC_CHNG_Q, Address 0x4E[4],
User Sub Map
When VDP_GS_VPS_PDC_UTC_CHNG_Q is 0 (default),
Gemstar, PDC, UTC, or VPS data is not detected.
When VDP_GS_VPS_PDC_UTC_CHNG_Q is 1, Gemstar,
PDC, UTC, or VPS data is detected.
VDP_VITC_Q, Address 0x4E[6], User Sub Map,
Read Only
When VDP_VITC_Q is 0 (default), VITC data is not detected.
When VDP_VITC_Q is 1, VITC data is detected.
Interrupt Status Clear Register Details
It is not necessary to write 0 to these write-only bits because
they automatically reset after they are set to 1 (self-clearing).
VDP_CCAPD_CLR, Address 0x4F[0], User Sub Map
Setting VDP_CCAPD_CLR to 1 clears the VDP_CCAP_Q bit.
VDP_CGMS_WSS_CHNGD_CLR, Address 0x4F[2],
User Sub Map
Setting VDP_CGMS_WSS_CHNGD_CLR to 1 clears the
VDP_CGMS_WSS_CHNGD_Q bit.
VDP_GS_VPS_PDC_UTC_CHNG_CLR,
Address 0x4F[4], User Sub Map
Setting VDP_GS_VPS_PDC_UTC_CHNG_CLR to 1 clears the
VDP_GS_VPS_PDC_UTC_CHNG_Q bit.
VDP_VITC_CLR, Address 0x4F[6], User Sub Map
Setting VDP_VITC_CLR to 1 clears the VDP_VITC_Q bit.
相關PDF資料
PDF描述
MAX3485ECSA+ IC TXRX RS485/422 10MBPS 8SOIC
VI-BWP-MX-F3 CONVERTER MOD DC/DC 13.8V 75W
VI-BWP-MX-F2 CONVERTER MOD DC/DC 13.8V 75W
VI-BWP-MW CONVERTER MOD DC/DC 13.8V 100W
VE-2W2-IW-F2 CONVERTER MOD DC/DC 15V 100W
相關代理商/技術參數(shù)
參數(shù)描述
ADV7180KCP32Z 功能描述:IC VIDEO DECODER 10BIT 32LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064
ADV7180KCP32Z-RL 功能描述:IC VIDEO DECODER 10BIT 32LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064
ADV7180KST48Z 功能描述:IC VID DECOD SDTV 10BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064
ADV7180KST48Z-RL 功能描述:視頻 IC 48-Lead Low Profile Quad Flat Package RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
ADV7180WBCP32Z 制造商:Analog Devices 功能描述:IC, 10-BIT 4X OVERSAMPLING SDTV DECODER 制造商:Analog Devices 功能描述:SDTV VIDEO DECODER 32-PIN LFCSP EP TRAY - Trays
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*