參數(shù)資料
型號： ADV7180BSTZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 26/116頁
文件大?。?/td> 0K
描述： IC VIDEO DECODER SDTV 64-LQFP
產(chǎn)品變化通告： ADV7180 Metal Mask Edit 22/Oct/2009
設(shè)計資源： Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060)
Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
標(biāo)準(zhǔn)包裝： 1
類型： 視頻解碼器
應(yīng)用： 數(shù)碼相機，手機，便攜式視頻
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： ADV7180BSTZ-REELDKR
Data Sheet
ADV7180
Rev. I | Page 17 of 116
48-LEAD LQFP
48
NC
47
HS
46
IN
TR
Q
45
V
S
/F
IE
LD
44
DV
DD
43
DG
ND
42
GP
O2
41
GP
O3
40
SC
L
K
39
SD
A
T
A
38
AL
S
B
37
R
E
SET
35
AIN5
34
AIN4
33
AIN3
30
VFEFN
31
AVDD
32
AGND
36
AIN6
29
VREFP
28
AGND
27
AIN2
25
PVDD
26
AIN1
2
DVDDIO
3
SFL
4
DVDDIO
7
P7
6
GPO0
5
GPO1
1
DGND
8
P6
9
P5
10
P4
12
P2
11
P3
NC = NO CONNECT
13
DG
ND
14
LL
C
15
NC
16
XT
A
L
1
17
XT
A
L
18
DV
DD
19
DG
ND
20
P1
21
PW
R
D
W
N
22
P0
23
AG
ND
24
EL
PF
PIN 1
ADV7180
LQFP
TOP VIEW
(Not to Scale)
05
70
0-
06
2
Figure 11. 48-Lead LQFP Pin Configuration
Table 12. 48-Lead LQFP Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
1, 13, 19, 43
DGND
G
Digital Ground.
2, 4
DVDDIO
P
Digital I/O Supply Voltage (1.8 V to 3.3 V).
3
SFL
O
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the
subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder.
5, 6, 41, 42
GPO0 to GPO3
O
General-Purpose Outputs. These pins can be configured via I2C to allow control of external devices.
7 to 12, 20, 22
P7 to P2, P1, P0
O
Video Pixel Output Port. See Table 100 for output configuration for 8-bit and 16-bit modes.
14
LLC
O
This is a line-locked output clock for the pixel data output by the ADV7180. It is nominally
27 MHz but varies up or down according to video line length.
15, 48
NC
No Connect Pins. These pins are not connected internally.
16
XTAL1
O
This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an external 1.8 V,
28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the crystal
must be a fundamental crystal.
17
XTAL
I
This is the input pin for the 28.6363 MHz crystal, or this pin can be overdriven by an external 1.8 V,
28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
18, 44
DVDD
P
Digital Supply Voltage (1.8 V).
21
PWRDWN
I
A logic low on this pin places the ADV7180 in power-down mode.
23, 28, 32
AGND
G
Analog Ground.
24
ELPF
I
The recommended external loop filter must be connected to the ELPF pin, as shown in Figure 59.
25
PVDD
P
PLL Supply Voltage (1.8 V).
26, 27, 33 to 36
AIN1 to AIN6
I
Analog Video Input Channels.
29
VREFP
O
Internal Voltage Reference Output. See Figure 59 for recommended output circuitry.
30
VREFN
O
Internal Voltage Reference Output. See Figure 59 for recommended output circuitry.
31
AVDD
P
Analog Supply Voltage (1.8 V).
37
RESET
I
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
38
ALSB
I
This pin selects the I2C address for the ADV7180. For ALSB set to Logic 0, the address selected
for a write is Address 0x40; for ALSB set to Logic 1, the address selected is Address 0x42.
39
SDATA
I/O
I2C Port Serial Data Input/Output Pin.
40
SCLK
I
I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.
45
VS/FIELD
O
Vertical Synchronization Output Signal/Field Synchronization Output Signal.
46
INTRQ
O
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video
47
HS
O
Horizontal Synchronization Output Signal.
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