Slave mode video interface (External cont" />
參數(shù)資料
型號(hào)： ADV601LCJSTZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 4/44頁(yè)
文件大?。?/td> 0K
描述： IC CODEC VIDEO DSP/SRL 120LQFP
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 視頻編解碼器
數(shù)據(jù)接口： DSP，串行
分辨率（位）： 8 b
三角積分調(diào)變： 無(wú)
電壓 - 電源，模擬： 4.5 V ~ 5.5 V
電壓 - 電源，數(shù)字： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 120-LQFP
供應(yīng)商設(shè)備封裝： 120-LQFP（14x14）
包裝： 帶卷 (TR)
ADV601LC
–12–
REV. 0
[5]
Video Interface Master/Slave Mode Select, M/S. This bit selects the following:
0
Slave mode video interface (External control of video timing, HSYNC-VSYNC-FIELD are inputs), reset value
1
Master mode video interface (ADV601LC controls video timing, HSYNC-VSYNC are outputs)
[6]
Video Interface 525/625 (NTSC/PAL) Mode Select, P/N. This bit selects the following:
0
525 mode video interface, reset value
1
625 mode video interface
[7]
Video Interface Encode/Decode Mode Select, E/D. This bit selects the following:
0
Decode mode video interface (compressed-to-raw)
1
Encode mode video interface (raw-to-compressed), reset value
[8]
Reserved (always write zero)
[9]
Video Interface Bipolar/Unipolar Color Component Select, BUC. This bit selects the following:
0
Bipolar color component mode video interface, reset value
1
Unipolar color component mode video interface
[10]
Reserved (always write zero)
[11]
Video Interface Software Reset, SWR. This bit has the following effects on ADV601LC operations:
0
Normal operation
1
Software Reset. This bit is set on hardware reset and must be cleared before the ADV601LC can begin processing. (reset value)
When this bit is set during encode, the ADV601LC completes processing the current field then suspends operation until the
SWR bit is cleared. When this bit is set during decode, the ADV601LC suspends operation immediately and does not resume
operation until the SWR bit is cleared. Note that this bit must be set whenever any other bit in the Mode register is changed.
[12]
HSYNC pin Polarity, PHSYNC. This bit has the following effects on ADV601LC operations:
0
HSYNC is HI during blanking, reset value
1
HSYNC is LO during blanking (HI during active)
[13]
HIRQ pin Polarity, PHIRQ. This bit has the following effects on ADV601LC operations:
0
HIRQ is active LO, reset value
1
HIRQ is active HI
[15:14] Reserved (always write zero)
FIFO Control Register
Indirect (Read/Write) Register Index 0x01
This register holds the service-request settings for the ADV601LC’s host interface FIFO, causing interrupts for the “nearly full” and
“nearly empty” levels. Because each register is four bits in size, and the FIFO is 512 positions, the 4-bit value must be multiplied by
32 (decimal) to determine the exact value for encode service level (nearly full) and decode service level (nearly empty). The ADV601LC
uses these setting to determine when to generate a FIFO Service Request related host interrupt (FIFOSRQ bit and FIFO_SRQ pin).
[3:0]
Encode Service Level, ESL[3:0]. The value in this field determines when the FIFO is considered nearly full on encode; a condi-
tion that generates a FIFO service request condition in encode mode. Since this register is four bits (16 states), and the FIFO is
512 positions, the step size for each bit in this register is 32 positions. The following table summarizes sample states of the
register and their meaning.
ESL Interrupt When . . .
0000 Disables service requests (FIFO_SRQ never goes HI during encode)
0001 FIFO has only 32 positions filled (FIFO_SRQ when >= 32 positions are filled)
1000 FIFO is 1/2 full, reset value
1111 FIFO has only 32 positions empty (480 positions filled)
[7:4]
Decode Service Level, DSL[7:4]. The value in this field determines when the FIFO is considered nearly empty in decode; a
condition that generates a FIFO service request in decode mode. Because this register is four bits (16 states), and the FIFO
is 512 positions, the step size for each bit in this register is 32 positions. The following table summarizes sample states of the
register and their meaning.
DSL Interrupt When . . .
0000 Disables service requests (FIFO_SRQ never goes HI)
0001 FIFO has only 32 positions filled (480 positions empty)
1000 FIFO is 1/2 empty, reset value
1111 FIFO has only 32 positions empty (FIFO_SRQ when >= 32 positions are empty)
[15:8]
Reserved (always write zero)
相關(guān)PDF資料
PDF描述
ADV202BBCZRL-115 IC CODEC VIDEO 115MHZ 121CSPBGA
VI-JNH-IX-S CONVERTER MOD DC/DC 52V 75W
VI-JN4-IX-S CONVERTER MOD DC/DC 48V 75W
AD1928YSTZ-RL IC CODEC 2ADC 8DAC W/PLL 48LQFP
VI-JN2-IX-S CONVERTER MOD DC/DC 15V 75W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV601LC-VIDEOPIPE 制造商:Analog Devices 功能描述:TOOLS:DEVELOPMENT BOARDS H/W 制造商:Analog Devices 功能描述:EVALUATION BOARD ((NS))
ADV601XS 制造商:Analog Devices 功能描述:
ADV611 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:CLOSED CIRCUIT TV DIGITAL VIDEO CODEC
ADV611JST 制造商:Analog Devices 功能描述:Video Compression 120-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:CLOSED CIRCUIT TV VIDEO CODEC - TQFP PKG - Tape and Reel
ADV611JSTZ 功能描述:IC CCTV DGTL VIDEO CODEC 120LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類(lèi)型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*