參數(shù)資料
型號： ADV601LCJSTZRL
廠商： Analog Devices Inc
文件頁數(shù)： 26/44頁
文件大?。?/td> 0K
描述： IC CODEC VIDEO DSP/SRL 120LQFP
標準包裝： 1,000
類型： 視頻編解碼器
數(shù)據(jù)接口： DSP，串行
分辨率（位）： 8 b
三角積分調(diào)變： 無
電壓 - 電源，模擬： 4.5 V ~ 5.5 V
電壓 - 電源，數(shù)字： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 120-LQFP
供應商設備封裝： 120-LQFP（14x14）
包裝： 帶卷 (TR)
ADV601LC
–32–
REV. 0
TIMING PARAMETERS
This section contains signal timing information for the ADV601LC. Timing descriptions for the following items appear in this
section:
Clock signal timing
Video data transfer timing (CCIR-656, and Multiplexed Philips formats)
Host data transfer timing (direct register read/write access)
Clock Signal Timing
The diagram in this section shows timing for VCLK input and VCLKO output. All output values assume a maximum pin
loading of 50 pF.
Table XVIII. Video Clock Period, Frequency, Drift and Jitter
Min VCLK_CYC
Nominal VCLK_CYC
Max VCLK_CYC
Video Format
Period
Period (Frequency)
Period
1, 2
CCIR-601 PAL
35.2 ns
37 ns (27 MHz)
38.9 ns
CCIR-601 NTSC
35.2 ns
37 ns (27 MHz)
38.9 ns
NOTES
1VCLK Period Drift =
± 0.1 (VCLK_CYC/field.
2VCLK edge-to-edge jitter = 1 ns.
Table XIX. Video Clock Duty Cycle
Min
Nominal
Max
VCLK Duty Cycle
1
(40%)
(50%)
(60%)
NOTE
1VCLK Duty Cycle = t
VCLK_HI/(tVCLK_LO) × 100.
Table XX. Video Clock Timing Parameters
Parameter
Description
Min
Max
Unit
tVCLK_CYC
VCLK Signal, Cycle Time (1/Frequency) at 27 MHz
(See Video Clock Period Table)
tVCLKO_D0
VCLKO Signal, Delay (when VCLK2 = 0) at 27 MHz
10
29
ns
tVCLKO_D1
VCLKO Signal, Delay (when VCLK2 = 1) at 27 MHz
10
29
ns
TEST CONDITIONS
Figure 18 shows test condition voltage reference and device
loading information. These test conditions consider an output
as disabled when the output stops driving and goes from the
measured high or low voltage to a high impedance state. Tests
measure output disable time (tDISABLE) as the time between the
reference input signal crossing +1.5 V and the time that the
output reaches the high impedance state (also +1.5 V). Simi-
larly, these tests conditions consider an output as enabled when
the output leaves the high impedance state and begins driving a
measured high or low voltage. Tests measure output enable time
(tENABLE) as the time between the reference input signal crossing
+1.5 V and the time that the output reaches the measured high
or low voltage.
INPUT
REFERENCE
SIGNAL
OUTPUT
SIGNAL
t
DISABLED
t
ENABLED
1.5V
VOH
VOL
VIH
VIL
1.5V
INPUT & OUTPUT VOLTAGE/TIMING REFERENCES
DEVICE LOADING FOR AC MEASUREMENTS
TO
OUTPUT
PIN
2pF
+1.5V
IOL
IOH
Figure 18. Test Condition Voltage Reference and Device Loading
相關PDF資料
PDF描述
ADV202BBCZRL-115 IC CODEC VIDEO 115MHZ 121CSPBGA
VI-JNH-IX-S CONVERTER MOD DC/DC 52V 75W
VI-JN4-IX-S CONVERTER MOD DC/DC 48V 75W
AD1928YSTZ-RL IC CODEC 2ADC 8DAC W/PLL 48LQFP
VI-JN2-IX-S CONVERTER MOD DC/DC 15V 75W
相關代理商/技術參數(shù)
參數(shù)描述
ADV601LC-VIDEOPIPE 制造商:Analog Devices 功能描述:TOOLS:DEVELOPMENT BOARDS H/W 制造商:Analog Devices 功能描述:EVALUATION BOARD ((NS))
ADV601XS 制造商:Analog Devices 功能描述:
ADV611 制造商:AD 制造商全稱:Analog Devices 功能描述:CLOSED CIRCUIT TV DIGITAL VIDEO CODEC
ADV611JST 制造商:Analog Devices 功能描述:Video Compression 120-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:CLOSED CIRCUIT TV VIDEO CODEC - TQFP PKG - Tape and Reel
ADV611JSTZ 功能描述:IC CCTV DGTL VIDEO CODEC 120LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*