參數(shù)資料
型號(hào)： ADV601LCJSTZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 32/44頁(yè)
文件大?。?/td> 0K
描述： IC CODEC VIDEO DSP/SRL 120LQFP
標(biāo)準(zhǔn)包裝： 1,000
類型： 視頻編解碼器
數(shù)據(jù)接口： DSP，串行
分辨率（位）： 8 b
三角積分調(diào)變： 無(wú)
電壓 - 電源，模擬： 4.5 V ~ 5.5 V
電壓 - 電源，數(shù)字： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 120-LQFP
供應(yīng)商設(shè)備封裝： 120-LQFP（14x14）
包裝： 帶卷 (TR)
ADV601LC
–38–
REV. 0
Host Interface (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Register Timing
The diagrams in this section show transfer timing for host read and write accesses to all of the ADV601LC’s direct registers, except
the Compressed Data register. Accesses to the Indirect Address, Indirect Register Data, and Interrupt Mask/Status registers are
slower than access timing for the Compressed Data register. For information on access timing for the Compressed Data direct regis-
ter, see the Host Interface (Compressed Data) Register Timing section. Note that for accesses to the Indirect Address, Indirect Reg-
ister Data and Interrupt Mask/Status registers, your system MUST observe ACK and RD or WR assertion timing.
Table XXVII. Host (Indirect Address, Indirect Data, and Interrupt Mask/Status) Read Timing Parameters
Parameter
Description
Min
Max
Unit
tRD_D_RDC
RD Signal, Direct Register, Read Cycle Time (at 27 MHz VCLK)
N/A
1
N/A
ns
tRD_D_PWA
RD Signal, Direct Register, Pulsewidth Asserted (at 27 MHz VCLK)
N/A
1
N/A
ns
tRD_D_PWD
RD Signal, Direct Register, Pulsewidth Deasserted (at 27 MHz VCLK)
5
N/A
ns
tADR_D_RDS
ADR Bus, Direct Register, Read Setup
2
N/A
ns
tADR_D_RDH
ADR Bus, Direct Register, Read Hold
2
N/A
ns
tDATA_D_RDD
DATA Bus, Direct Register, Read Delay
N/A
171.6
2, 3
ns
tDATA_D_RDOH
DATA Bus, Direct Register, Read Output Hold (at 27 MHz VCLK)
26
N/A
ns
tRD_D_WRT
WR Signal, Direct Register, Read-to-Write Turnaround (at 27 MHz VCLK)
48.7
4
N/A
ns
tACK_D_RDD
ACK Signal, Direct Register, Read Delayed (at 27 MHz VCLK)
8.6
287.1
5, 6
ns
tACK_D_RDOH
ACK Signal, Direct Register, Read Output Hold (at 27 MHz VCLK)
11
N/A
ns
NOTES
1
RD input must be asserted (low) until ACK is asserted (low).
2Maximum t
DATA_D_RDD varies with VCLK according to the formula: t DATA_D_RDD (MAX) = 4 (VCLK Period) +16.
3During STATS_R deasserted (low) conditions, t
DATA_D_RDD may be as long as 52 VCLK periods.
4Minimum t
RD_D_WRT varies with VCLK according to the formula: t RD_D_WRT (MIN) = 1.5 (VCLK Period) –4.1.
5Maximum t
ACK_D_RDD varies with VCLK according to formula: t ACK_D_RDD (MAX) = 7 (VCLK Period) +14.8.
6During STATS_R deasserted (low) conditions, t
ACK_D_RDD may be as long as 52 VCLK periods.
VALID
(I) ADR,
BE, CS
(I)
RD
(O) DATA
(O)
ACK
(I)
WR
t
ADR_D_RDS
t
ACK_D_RDOH
t
RD_D_RDC
t
RD_D_PWA
t
RD_D_PWD
t
ADR_D_RDH
t
DATA_D_RDD
t
DATA_D_RDOH
t
RD_D_WRT
t
ACK_D_RDD
Figure 28. Host (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Read Transfer Timing
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